The Xillybus Forum

Hello,

This is most likely not a problem. A similar warning for the xillybus_S_AXI interface is muted to Info level by the initialization script. It seems like Vivado 2017.2 produces the warning on xillybus_S_AXI instead, which is currently not muted. That's why it appeared as a Critical Warning to you.

On Vivado 2017.3, this warning disappears altogether.

So if the system boots up find, and /dev/xillybus_* files appear, you can safely ignore this warning.

Regards,
Eli

Hi,

I downloaded the xilinux-eval-zybo-2.0c for Vivado 2017.2 run over Ubuntu 16.04 platform but it pops up the following message. Is is as your expectation ? What should user do ?

[BD 41-968] AXI interface port /xillybus_M_AXI is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port.