The Xillybus Forum

Hello,

The guide is maybe somewhat misleading: It's indeed recommended to replace the files when the FPGA platform is one for which there is an explicit example for. Zynq isn't one of these (spartan6, for example, is an FPGA family from Xilinx). So what you attempted didn't have a chance, unfortunately. The change has to be done manually.


However if you read through the example code, it shouldn't be too difficult to figure out how to edit your xillydemo.vhd. You may even download the evaluation code for Spartan 6 and compare.

Hope this will go smooth from here on.

Regards,
Eli

Hello,

I discovered Xillybus a few days ago and have been working wiht it, but I am still a little confused about some stuff.

I got a Zedboard and sucefully installe the Xillinux demo bundle. I generated the bitstrem with Vivado 2015.2 on Windows 10 and made the SD partitions on Ubuntu 14.04. Everthing worked just fine and I was able to test the all the examples of the guide "Getting started with Xillybus on a Linux host" section 4.

Now I am trying to implemente xillycapure as "Xillybus FPGA designer’s guide" section 4, but I have not been able to generate the new bitstream.

I have followed section 4.2

[quote]
The recommended procedure is to remove the existing xillydemo.v(hd) from the project
as well as the UCF file. Then add xillycapture.v(hd) to the project, and only after that,
re-add the UCF file to the project. ISE may disregard the UCF file otherwise.
[/quote]

The procedure I followed is:
1- I open Vivado 2015.2 on my Windows 10.

2- Click of Tools > Run Tcl Script... and chose ".../xillinux-eval-zedboard-1.3c/vhdl/xillydemo-vivado.tcl" click ok and Vivado makes its magic. So far, so good.

3- I remove xillydemo.vhd as stated in the guide:

[img]http://i.imgur.com/7wL5xva.png[/img]

4 - I remove the constrain file, in this case it is a XDC file.

[img]http://i.imgur.com/9kpSD5C.png[/img]

5- Then, I include the ".../xillycapture/spartan6/xillycapture.vhd" file and ".../xillycaptur/async_fifo_32.xco":

[img]http://i.imgur.com/sDb03hv.png[/img]

6- I re-add the contraint file ".../xillinux-eval-zedboard-1.3c/vivado-essentials/xillydemo.xdc":

[img]http://i.imgur.com/tDuvYCo.png[/img]

7- Finally I re-name the top module as "xillycapture"

[img]http://i.imgur.com/BB01sOo.png[/img]

8- The next step would be to generate bitstrem.

It runs for minutes for about 10, the Design Runs shows that "Out-of-Context Module Runs" are generated correctly first, then in "synth_1" it fails:

[img]http://i.imgur.com/H9d43dS.png[/img]

The errors I got are something like this:

[img]http://i.imgur.com/DvNttFY.png[/img]


I would really appreciate some help here, I do not really know how to implement this xillycapture.

Thanks in advance.