by support »
Well, the usual situation is that there is a PCIe module supplied by your FPGA vendor, which your application logic module interacts with. Among others, the PCIe module has a way of telling you what the max_payload_size is (some dedicated pins, or you need to scan the configuration space). Each PCIe module has its own method for that, so it's down to reading its user guide.
The max_payload_size is a figure which is negotiated between the host and PCIe endpoint, so even though it almost always ends up 128 bytes, there is no way to know it in advance.
It is then the application logic's responsibility to make sure that no data-carrying TLP has more than max_payload_size bytes of data in it. This holds for write data packets and completions of read requests alike.
Eli
Well, the usual situation is that there is a PCIe module supplied by your FPGA vendor, which your application logic module interacts with. Among others, the PCIe module has a way of telling you what the max_payload_size is (some dedicated pins, or you need to scan the configuration space). Each PCIe module has its own method for that, so it's down to reading its user guide.
The max_payload_size is a figure which is negotiated between the host and PCIe endpoint, so even though it almost always ends up 128 bytes, there is no way to know it in advance.
It is then the application logic's responsibility to make sure that no data-carrying TLP has more than max_payload_size bytes of data in it. This holds for write data packets and completions of read requests alike.
Eli