The Xillybus Forum

Thank you for the reply.
Could you please suggest me some forums wherein I can inquire about this issue? I have tried referring the spec but it contains no info regarding this.

Hi,

Unfortunately, I'm not that familiar with the physical layer to answer your question. I suppose the answer lies somewhere in the specs. Or maybe someone else will answer this in the future.

Regards,
Eli

Hi Eli,

Thank you for the highly informative forum. I have a doubt regarding the data ordering in the Phy Layer. I wanted to know if the COM character can come only on the start boundary of DWORDS or can come in between the DWORDS as well when Ordered Sets are sent. Put in another way, if the Phy has a 32 bit datapath internally must it detect each of the 4 bytes for start of Ordered Sets or will the COM always be byte 0 or byte 4 as per implementation (considering PCIe 1.0 or 2.0 with 8b/10b)? Also if I connect a 4 lane PCIe device as a Single Lane enabled device will the number of Logical Idles still be a multiple of 4 or could it be any random number?

Thanks in advance.