by support »
Hi,
There are indeed three address spaces for a PCI/PCIe device:
- The configuration space contains a data structure, which informs the host about the device's capabilities and status. The host sets some registers in this address space to configure the device (in particular, it assigns the device's bus address and BAR regions by writing to these registers).
- The memory space is where accesses take place when the host performs a memory read or write, as in plain C's *addr = data, where addr points at an address that is mapped to the device.
- The I/O space is a legacy support feature, which allows backward compatibility with rather ancient peripherals. For example, the parallel port 0 is traditionally mapped to I/O ports 0x378-0x37a. No new design should rely on this space. Peripherals mapped to the I/O space are usually implemented directly on the processor itself or its companion chip.
Aside from being an ancient leftover, the I/O space requires an inp or outp opcode in x86 assembly language, and may not be supported at all by non-x86 processors. And unlike a memory space write, writes to I/O ports require that the processor waits until the device acknowledges the read (by sending a completion on the PCIe bus). In terms of today's processors, that slows down things considerably. Writing to memory space, on the other hand, is fire-and-forget (i.e. a posted transaction).
So the bottom line is that I/O space should be used only for the sake of following an already established convention on how to access that type of device. Otherwise there is no reason to use it.
Regards,
Eli
Hi,
There are indeed three address spaces for a PCI/PCIe device:
[list]
[*]The configuration space contains a data structure, which informs the host about the device's capabilities and status. The host sets some registers in this address space to configure the device (in particular, it assigns the device's bus address and BAR regions by writing to these registers).
[*]The memory space is where accesses take place when the host performs a memory read or write, as in plain C's *addr = data, where addr points at an address that is mapped to the device.
[*]The I/O space is a legacy support feature, which allows backward compatibility with rather ancient peripherals. For example, the parallel port 0 is traditionally mapped to I/O ports 0x378-0x37a. No new design should rely on this space. Peripherals mapped to the I/O space are usually implemented directly on the processor itself or its companion chip.[/list]
Aside from being an ancient leftover, the I/O space requires an inp or outp opcode in x86 assembly language, and may not be supported at all by non-x86 processors. And unlike a memory space write, writes to I/O ports require that the processor waits until the device acknowledges the read (by sending a completion on the PCIe bus). In terms of today's processors, that slows down things considerably. Writing to memory space, on the other hand, is fire-and-forget (i.e. a posted transaction).
So the bottom line is that I/O space should be used only for the sake of following an already established convention on how to access that type of device. Otherwise there is no reason to use it.
Regards,
Eli