PCIe in loopback

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Re: PCIe in loopback

Post by support » Fri Mar 01, 2019 12:59 pm

Hello,

Looping back is perfectly fine with Xillybus IP core. You seem to refer to the guideline not to loop back in bandwidth tests:

http://xillybus.com/doc/bandwidth-guidelines

When just looping back in the FPGA, Xillybus' IP core both fills and empties the FIFO in the middle very rapidly. There is however a latency between the moment a data transaction is possible to when it's carried out, which leads to a very uneven data transport. This, in turn, yields suboptimal bandwidth performance.

As this is a very artificial test case, the core isn't optimized to handle it better. It therefore makes no sense to test it for bandwidth this way.

Regards,
Eli

Re: PCIe in loopback

Post by kevin » Fri Mar 01, 2019 8:14 am

Sorry, I have a typo mistake in the first post above.

Loopback setup actually slow things down by 50 percent. Why ?

PCIe in loopback

Post by Guest » Fri Mar 01, 2019 7:58 am

May I know why connecting PCie in loopback is not recommended ?

Loopback setup does not actually slow things down.

I have confirmed this with actual loopback setup, may I know WHY loopback setup has the almost similar throughput result with regards to the theoretical throughput result for one-way (simplex) direction ?

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