Simulation of PCIE commuication

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Re: Simulation of PCIE commuication

Post by lucadimauro » Sat Jan 09, 2021 10:18 am

Thank you Eli for your reply. It is very useful.
I haven't checked that guide because I'm still learning the functionalities of Xillybus.

I'll read the API giude.

Best,
Luca

Re: Simulation of PCIE commuication

Post by support » Fri Jan 08, 2021 8:39 am

Hello,

The /dev/xillybus_* files appear only when you have an FPGA loaded with the relevant bitstream file, and it's connected to the PC. Plus the driver should be installed, but it usually is. As you don't have any FPGA, there's no reason you should see those files.

As for simulation practices with Xillybus, please refer to section 5 of the "Xillybus FPGA designer’s guide":

http://xillybus.com/downloads/doc/xillybus_fpga_api.pdf

Regards,
Eli

Simulation of PCIE commuication

Post by lucadimauro » Fri Jan 08, 2021 8:21 am

Hello,
I'm trying to perform some tests regarding simulation of the communication between an FPGA and an host PC over a PCIE bus. To simulate the FPGA I use ModelSim-Altera and Quartus II Lite Edition.
I downloaded the Xillybus demo an synthetized succesfully, but I still don't see any
Code: Select all
/dev/xillybus_something
device file.

I do these tests with the university, so I cannot buy yet an FPGA and my PC doesn't have a PCIE port natively.
I use Ubuntu 20.04 as host OS.

Is it reasonable to do such test? Can you provide me some tips?

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