by support »
Hello,
Given that Kintex 7 devices with -1 speed grade have no problem with Gen2, I take it that the purpose of this change is to reduce the bus_clk frequency from 250 MHz to 125 MHz, and by doing so, solve a timing constraint issue.
So to answer your question, none of the IP cores care about what happen with the PCIe block (as long as it works), so reducing the lane count and/or speed will work fine. The reduction of the frequency is fine as well.
I should mention however that if there's a chance that a license will be purchased for this core in the future, you should consider a rev. B core, as the price for XL is generally higher (even though not dramatically).
Another thing is that reverting to rev. B might by itself solve the timing problem, because the XL core is heavier and consumes more routing resources. But I can't tell if that will help.
As for your second question, I suppose you meant staying at x8 and move to Gen1. If you don't meet timing, where are the failing paths? If they are outside the PCIe block, then you probably haven't done the transition correctly, because the whole point is to reduce bus_clk. However if they are inside the PCIe block, I would suggest trying to set up Xilinx' demo design for PCIe with these parameters, and see if that passes timing. If not, there's probably not much to do.
Regards,
Eli
Hello,
Given that Kintex 7 devices with -1 speed grade have no problem with Gen2, I take it that the purpose of this change is to reduce the bus_clk frequency from 250 MHz to 125 MHz, and by doing so, solve a timing constraint issue.
So to answer your question, none of the IP cores care about what happen with the PCIe block (as long as it works), so reducing the lane count and/or speed will work fine. The reduction of the frequency is fine as well.
I should mention however that if there's a chance that a license will be purchased for this core in the future, you should consider a rev. B core, as the price for XL is generally higher (even though not dramatically).
Another thing is that reverting to rev. B might by itself solve the timing problem, because the XL core is heavier and consumes more routing resources. But I can't tell if that will help.
As for your second question, I suppose you meant staying at x8 and move to Gen1. If you don't meet timing, where are the failing paths? If they are outside the PCIe block, then you probably haven't done the transition correctly, because the whole point is to reduce bus_clk. However if they are inside the PCIe block, I would suggest trying to set up Xilinx' demo design for PCIe with these parameters, and see if that passes timing. If not, there's probably not much to do.
Regards,
Eli