The Xillybus Forum

Hello,

I take it that you're talking about xillybus_mem_8 in Xillybus' demo bundle.

Yes, the address' width in this case is 5 bits, so the memory wraps after 32 entries. To get a larger space, please generate a custom IP core in the IP Core Factory, with whatever address space necessary. You'll also have to modify xillydemo.v/.vhd to accommodate a larger memory.

Regards,
Eli

Hello Eli,

First, thanks for the great support..

I would like to ask a question.. maybe an easy one.. In verilog code, memory buffer size is fixed to 32.. even if I change this value to 128, from the host side, I keep reading the first 32 [0-31] and the rest is the copy of that in a from of [32-63, 64-95 ..] .. Am i doing something wrong? I suspect that internally the address is masked up to 32.

Thanks,

-Oz