by support »
Hi,
This forum is dedicated to Xillybus-specific issues. You should ask your question is forums related to FPGA designs in general.
Anyhow, lookup tables can be made in several ways. It depends on taste and style. If you generate a block RAM core in ISE or Vivado, you can pick its initial values, possibly to be read from a file. If you don't write to this RAM, you have a ROM, which can be used as a lookup table. It's also possible to set the initial values with instantiation parameters.
There are also several techniques for an inferred lookup table. An example in Verilog can be seen on this page:
http://billauer.co.il/blog/2009/03/xst- ... sizer-bug/Never mind the bug, which is most likely fixed a long time ago. The Verilog code outlines an example.
But again, this is not related to Xillybus, so you'll get much better answers elsewhere.
Regards,
Eli
Hi,
This forum is dedicated to Xillybus-specific issues. You should ask your question is forums related to FPGA designs in general.
Anyhow, lookup tables can be made in several ways. It depends on taste and style. If you generate a block RAM core in ISE or Vivado, you can pick its initial values, possibly to be read from a file. If you don't write to this RAM, you have a ROM, which can be used as a lookup table. It's also possible to set the initial values with instantiation parameters.
There are also several techniques for an inferred lookup table. An example in Verilog can be seen on this page:
http://billauer.co.il/blog/2009/03/xst-rom-case-synthesizer-bug/
Never mind the bug, which is most likely fixed a long time ago. The Verilog code outlines an example.
But again, this is not related to Xillybus, so you'll get much better answers elsewhere.
Regards,
Eli