by support »
Hello,
Yes, Xillybus offers seekable streams, which have address lines on the FPGA side. These can be seamlessly connected to synchronous RAMs on the FPGA, or to anything that emulates a synchronous RAM -- in particular a register/data interface with wr_en, rd_en address, data and clock.
Please refer to the examples for memread and memwrite in the documentation. The FPGA demo bundle includes such a memory interface already (xillybus_mem_8).
Regards,
Eli
Hello,
Yes, Xillybus offers seekable streams, which have address lines on the FPGA side. These can be seamlessly connected to synchronous RAMs on the FPGA, or to anything that emulates a synchronous RAM -- in particular a register/data interface with wr_en, rd_en address, data and clock.
Please refer to the examples for memread and memwrite in the documentation. The FPGA demo bundle includes such a memory interface already (xillybus_mem_8).
Regards,
Eli