The Xillybus Forum

Hello Eli,

this line of you answer

When the Xillybus stream is 32 bit wide, the driver treats the data as an array of unsigned int. In other words, it groups the buffer into segments of 4 bytes each, and makes a 32-bit word of each

is what i had in mind. But because it wasn't clear from the documentation i wanted some kind of confirmation. And as you mentioned my purpose is to use a dual clock asymmetric FIFO in my design for sending data from Xillybus to my logic .

Regards.

Hello,

write() accepts a pointer to a buffer, with no knowledge on how the data in it is organized. It's therefore meaningless that the buffer was defined as char array in the C program.

When the Xillybus stream is 32 bit wide, the driver treats the data as an array of unsigned int. In other words, it groups the buffer into segments of 4 bytes each, and makes a 32-bit word of each. If you happened to define the buffer as unsigned int my_buffer[32], and fill it with integers in your programs, the same integers will appear on the FPGA side in the respective *_data vector (treated as a plain 32-bit word).

But this stream could also be used to efficiently transport data in any other format, given that you handle the packing and unpacking properly. Which is usually quite simple. For example, if you use an asymmetric FIFO on the FPGA side (8 bits wide on one side, 32 bits on the side going to the Xillybus core) the reorganization of the data will turn out right.

Regards,
Eli

Hello,

i am a bit confused about the relation between the data width of a stream to the buffer type used in a write() or read() operation. For example suppose that i have a 32bit wide host to fpga stream and in my program i defined a buffer variable as
unsigned char my_buffer[128]. After assigning values to the buffer and call write(fd,my_buffer,sizeof(my_buffer)) the data go to a DMA buffer. How does Xillybus transmit the data to my logic? Does it transmit each my_buffer[i] adding zeros in front to match 32bit width