The Xillybus Forum

Hi Eli,

Thank you very much for the reply. I see it is not worth continuing in that direction.
This is my first attempt to do anything with FPGAs, so I did not know
the right direction and tried to go with anything new available. My application is
to connect and ADC6445 board with Xilinx SP605 and the xillybus is of great help.
Thanks again.
JK

Hello,

There is much more to a PCIe block version that just the signal names. By attempting to modify the connection between the Xillybus IP core and Xilinx' PCIe block, you're risking to lose the reliability that Xillybus offers. Subtle differences in how the block behaves can be the difference between a system you can trust and one that fails every now and then.

In your case, which I consider lucky, you probably got something wrong enough so that the FPGA didn't respond to the host's first request for a life sign.

Which bring me to ask: Why did you attempt to upgrade to PCIe block in the first place?

Regards,
Eli

Hi,

I could use xillybus with Xilinx pcie version 1.3. I tried connecting it with
version 2.4, after translating the names of the signals in a wrapper module.
With this setup, when I load the kernel module it gives me an error
"No response from FPGA. Aborting." Where could be the problem?
Is it possible to work with pcie v2.4?

Regards
JK