The Xillybus Forum

Thanks Eli,

I'll try that ! :D

Hello,

Please refer to section 4.3.3 in the "Getting started with the FPGA demo bundle for Xilinx" guide:

http://xillybus.com/downloads/doc/xillybus_getting_started_xilinx.pdf

You may generate Xilinx' PCIe block under ISE 13.1, and use the Verilog files in the project in any later ISE version. There's no problem having two versions of ISE on the same computer (or you could even run ISE 13.1 on another computer, since it's a one-off task).

Regards,
Eli

Hello Mr.Eli,

Do you have a precompiled xillybus core that I can use for virtex 5 in and implement in xilinx ISE 14.5 directly ? I'd be using this for research purposes only.

Thank you,
Mugundhdan