The Xillybus Forum

Hello,

If you refer to the demo bundle as is, you'll see in xillydemo.v/vhdthat there's a FIFO looping back from write_8 to read_8. So that's where the data written to xillybus_write_8 goes. In order to access the data, grab it from the FIFO instead of the connections to the Xillybus' read_8 related ports.

As for mem_8 and seekable streams in general, please note in the xillydemo.v/vhd that it also has an address port. This presents a standard synchronous data/address interface, so a block RAM or something that mimics the behavior of a block RAM can be attached (e.g. a register interface). The example in xillydemo.v/vhd demonstrates this.

So if you prefer to control your logic by writing to registers, I suppose the "address/data interface" is more suitable. If you want to send commands that the logic interprets from a stream, the "command and status" is probably more suitable.

Regards,
Eli

Hello,
My project is to achieve a DAQ system ,acquire data from the transducers used for ultrasound imaging.I'am using artix-7(AC701) fpga board with Xillybus.

I want to send some configuration information to FPGA and get a frame,like sample rate,sample time,etc.Then FPGA get these info and do data acquistion.

My question is ,what is the destination when send these info into FPGA?
what is the difference between xillybus_write_8 and xillybus_mem_8?

When I generate IP Core,in the spinner of Use,
what is the difference between "command and status" and "address/data interface",which item should I choose?

Regards,
coke