How many bits wide?

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Re: How many bits wide?

Post by helmutforren » Mon May 07, 2018 1:56 pm

Cool! Didn't know you could do that. It appears you took my post to one forum thread and moderated/approved it only my new question I couldn't see yet, as the answer. Your lack of comment tells me, "hey you dummy, you just answered your own question! 'Nuf said." (In a kind way, of course.) Thanks.

Re: How do I make device look like standard serial port

Post by helmutforren » Mon May 07, 2018 1:46 pm

Eli, I can't edit my recent fifo width post, of course, because it hasn't been moderated yet. So I'll comment here.

I went to the IP Core Factory as a guest. I see where I can specify 32-, 16-, or 8-bit wide, and I see that I can mix those per the example bundle. This means I can do serial with 8-bit width and other things with 32-bit width. I believe I now have my own answer to the question.

How many bits wide?

Post by helmutforren » Mon May 07, 2018 1:32 pm


I don't have access to hardware or Xillybus yet, but I need to plan.

I'm anticipating a 32-bit wide architecture inside my FPGA. I'd like to interface with Xillybus using 32-bit wide FIFOs. Then, I guess, on the Linux side, the named pipes will be character devices that read/write 8 bits at a time, presumably in groups of 4 to get up to 32 bits.

Here are my questions.

1) Will the above paragraph work? That is, can I make the Xillybus FIFOs 32-bits wide?

2) Can somebody else on my FPGA use a different FIFO width?

3) Those serial ports of mine on Rx might receive a number of chars not a multiple of 4. This brings up a flushing and valid byte issue. Does Xillybus already have a solution for this issue?

4) Alternatively, could I make these Xillybus FIFOs 8-bits wide (mixing width where some are 8-bits, others are 32-its)?

5) Can

Thanks very much