by support »
Hello,
The next step is to write logic in Verilog or VHDL that samples the data from the ADC and writes each sample to a FIFO in the FPGA that is connected to the Xillybus IP core on its other side. Once you have this set up, you can copy the data into a file on the host with something like:
cat /dev/xillybus_read_32 > samples.dat
Getting the logic working correctly is usually the difficult part of the project, however it's out of this forum's scope. I suggest turning to Xilinx' or Intel's forums for assistance on these matters.
Regards,
Eli
Hello,
The next step is to write logic in Verilog or VHDL that samples the data from the ADC and writes each sample to a FIFO in the FPGA that is connected to the Xillybus IP core on its other side. Once you have this set up, you can copy the data into a file on the host with something like:
cat /dev/xillybus_read_32 > samples.dat
Getting the logic working correctly is usually the difficult part of the project, however it's out of this forum's scope. I suggest turning to Xilinx' or Intel's forums for assistance on these matters.
Regards,
Eli