Using Revision B/XL/XXL in the demo bundle

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Topic review

Expand view Topic review: Using Revision B/XL/XXL in the demo bundle

Re: Using Revision B/XL/XXL in the demo bundle

Post by support »


Revision B/XL/XXL IP cores are not open for download by default because they require a slightly higher awareness of some technical details.

In particular, the XL and XXL IP cores can't be used with the original demo bundle that is available at the website. You need to decide which you need, and request the relevant bundle. This is mentioned in the response mail to an IP Core Factory account upgrade to cover B/XL/XXL, as well as on this page:

Revision B IP cores can be used as drop-in replacements for the openly available revision A.

Another thing is that the blockdesign flow is probably not the correct choice for a data acquisition project. Actually, it's generally not recommended -- the only scenario it is expected to make sense is in conjunction with HLS. Odds are that it will be more difficult to work with the block design overall, despite the inviting quick graphical interface.

Also, you've selected an XXL core, but it seems like an XL core will suffice. There is no problem with a 256-bit interface with the user logic with revision B and XL. If you don't need a bandwidth over 3.5 GB/s, going for XXL is just going to make the design heavier.

I suggest considering which revision of the IP core you want to work with, and request the necessary demo bundle (via direct email).


Using Revision B/XL/XXL in the demo bundle

Post by tomyam9 »


Sorry, let me ask a rudimentary question.

I want to use custom Revision XXL Xillybus IP cores in a block design of xillydemo-vivado.

My device is "Xilinx Virtex-7 FPGA VC709 Connectivity Kit" which is connected to host PC installed Ubuntu 18.04.1 LST.

I have already downloaded "Xillybus for PCIe" for VC709 (xillybus-eval-virtex7-gen3-2.0d) from the download page.
Then, by running xillydemo-vivado.tcl under "blockdesign" file on Vivado 2019.1.3, I generated a block design of xillydemo, and the bit stream generated from it runs normally on my device.
I confirmed that writing and reading using "/dev/xillybus_read_8" and "/dev/xillybus_write_8" files can be performed on the host PC.

Then, I wanted to apply a custom IP core of Revision XLL acquired from The Custom IP Core Factory to xillydemo.

I have added the following Device files to this core:
    [Name/Direction/Data width/Expected BW/Autoset/Details]

    xillybus_read_256 /Upstream (FPGA to host)/256 bits / 3200 MB/s /Yes/Data acquisition / playback (10 ms)

    xillybus_write_256/Downstream(host to FPGA)/256 bits/ 3200 MB/s/Yes/Data acquisition / playback (10 ms)

I downloaded it and ran "insertcore.tcl" in "xillybus_block" folder on the design block of xillydemo.
An IP core on the block design is updated successfully, but a file containing the "pcie_v7_8x_xxl" module required in xillybus_block.v cannot be found and the bit stream cannot be generated.

Although the existence of the "pcie_v7_8x.v " file containing the" pcie_v7_8x "module can be confirmed, but it seems that the bit width of several wires ore register do not match and it cannot be used as it is.

Did something go wrong with my steps?

Please tell me how to make it work on xillydemo.