VC707 board with Xillybus on PCIe GEN3

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Expand view Topic review: VC707 board with Xillybus on PCIe GEN3

Re: VC707 board with Xillybus on PCIe GEN3

Post by support » Fri Feb 28, 2020 8:36 am


The problem you describe is related to Xilinx' PCIe block. I would suggest trying Gen1, Gen2 and Gen3, possibly change the lane count as well as the device's identification info, in particular the Class. Creating an example design from the existing PCIe block in Xillybus' design can be a good start. See if the device enumerates.

Once you've figured out what the problem is and found a solution, you may migrate it into Xillybus' design. There is a section in the Getting Started guide for Xilinx on making changes to the physical parameters, if necessary.

What you definitely can't change, is the width of the data signals between the PCIe block and Xillybus' IP core. Actually, you can, but that requires another Xillybus IP core revision.

Xillybus' IP core doesn't care about the parameters of the PCIe block. However changes in the PCIe block's parameter might require changes in the design's timing constraints, which is the delicate part in this whole manner.

And another thing to be aware of: There is an annoying bug (or is it a feature?) that Vivado's GUI resets the device's Vendor / Product IDs to default every time some change is made to the parameters. That too can lead to some confusion.


Re: VC707 board with Xillybus on PCIe GEN3

Post by tozkoparan » Fri Feb 28, 2020 8:22 am

Hello again

Thank you for your answer

If we want to generate sample designs from scratch what are the settings that we can change?
Are they the setting belonging to Xillybus IP generation or are they the settings of the PCI core of Xilinx that we put in Xillybus IP?

best regards

Re: VC707 board with Xillybus on PCIe GEN3

Post by support » Fri Feb 28, 2020 8:09 am


The Xillybus demo bundle for VC707 has the PCIe lanes set to Gen1, as there is no advantage in setting them at a higher rate: The 800 MB/s limit of the rev A core is below what the physical lanes can pass through anyhow.

Therefore, the actual link will always run at Gen1, regardless of the computer's PCIe version. Gen2 and Gen3 hosts must support Gen1 for the sake of backward compatibility.

Some computers don't work properly with Gen1 devices due to poor design, and in the past some BIOSes have rejected Xillybus' PCIe interface because it reports itself as class 0xff, which means "unknown class". This is the correct setting for a PCIe device that doesn't fit into the list of standard functionalities, and yet some computers won't enumerate such devices. It's effectively a bug in the BIOS.

The easiest way to figure out why the board isn't detected is to generate sample designs for the PCIe from scratch, each time with a different PCIe block setting. This is likely to reveal what your specific hardware doesn't like.

I would also consider working with a different computer, if that is possible. Failing to meet the PCIe spec isn't necessarily a good sign.


VC707 board with Xillybus on PCIe GEN3

Post by tozkoparan » Fri Feb 28, 2020 7:48 am


Up to this time, we were using our VC707 board with Xillybus on PCs with PCIe GEN2 slots.
Is it possible to use the VC707 board with Xillybus on PCs with PCIe GEN3 slots?

When we connect our VC707 board with Xillybus IP implemented to a PCIe GEN3 slot the PC does not recognize Xillybus.
Therefore we cannot install Xillybus driver on PC

thank you

best regards