by support »
Hello,
You probably don't want to go that path. It involves the following steps (at least, I might have missed something): Build the project on XPS, change the FPGA1 clock in the project's setting, derive the BSP from it, generate and compile the FSBL accordingly and recompile U-boot along with the new FSBL, and rebuild boot.bin accordingly. Then change the same clock's setting in the Vivado project (I suppose you work with Vivado?) and build the project as usual.
To get this working, you'll probably need to download the ISE suite (for XPS) and learn how to work with the ARM cross compiler.
So it's quite a long way to go.
Now, odds are that you want to reduce bus_clk because it fails to meet constraints on your own logic. That's easily solved: You may use dual-clock ("asynchronous") FIFOs instead of the single-clock FIFOs in the demo project. This allows you to work with any clock you like for your own logic, and connect that clock to the FIFO for driving the side that talks with your logic.
Just a word of notice: Assuming that you're working with Vivado, make sure to create clock group constraints for the two clocks, declaring that they're independent, or timing may fail based upon timing between the paths (which should be ignored).
Regards,
Eli
Hello,
You probably don't want to go that path. It involves the following steps (at least, I might have missed something): Build the project on XPS, change the FPGA1 clock in the project's setting, derive the BSP from it, generate and compile the FSBL accordingly and recompile U-boot along with the new FSBL, and rebuild boot.bin accordingly. Then change the same clock's setting in the Vivado project (I suppose you work with Vivado?) and build the project as usual.
To get this working, you'll probably need to download the ISE suite (for XPS) and learn how to work with the ARM cross compiler.
So it's quite a long way to go.
Now, odds are that you want to reduce bus_clk because it fails to meet constraints on your own logic. That's easily solved: You may use dual-clock ("asynchronous") FIFOs instead of the single-clock FIFOs in the demo project. This allows you to work with any clock you like for your own logic, and connect that clock to the FIFO for driving the side that talks with your logic.
Just a word of notice: Assuming that you're working with Vivado, make sure to create clock group constraints for the two clocks, declaring that they're independent, or timing may fail based upon timing between the paths (which should be ignored).
Regards,
Eli