by support »
Hello,
This question should be asked in Xilinx' forum, and not here, as it relates to understanding rather basic VHDL concepts. But since we're at it, here's the example code from xillydemo.vhd explained:
- Code: Select all
process (user_clk)
begin
if (user_clk'event and user_clk = '1') then
if (user_wstrb(0) = '1') then
litearray0(lite_addr) <= user_wr_data(7 DOWNTO 0);
end if;
The process (user_clk) + if (user_clk'event and user_clk = '1') part is a template, which together means that the statements that follow should happen on a rising edge of user_clk. The mix-and-match you've done between a process on user_clk and a rising edge of user_wren has no proper translation into logic, and breaks the rules of synchronous design. In particular because you never ever want to detect a rising edge of anything else than a clock or a dedicated asynchronous signal, like a reset (it's about glitches).
The if (user_wstrb(0) = '1') part checks the state of user_wstrb's bit 0 at the event of a rising clock (because of the foregoing process / if), and if it's 1, then the register is updated, on that rising clock. Actually, it's an array, so we get a synchronous RAM.
I'm not sure how much this helped. What you really need is to grasp the basics of synchronous design with VHDL, and the xillydemo.vhd example will be crystal clear. That's where I would put the money if I were you.
Regards,
Eli
Hello,
This question should be asked in Xilinx' forum, and not here, as it relates to understanding rather basic VHDL concepts. But since we're at it, here's the example code from xillydemo.vhd explained:
[code]
process (user_clk)
begin
if (user_clk'event and user_clk = '1') then
if (user_wstrb(0) = '1') then
litearray0(lite_addr) <= user_wr_data(7 DOWNTO 0);
end if;
[/code]
The process (user_clk) + if (user_clk'event and user_clk = '1') part is a template, which together means that the statements that follow should happen on a rising edge of user_clk. The mix-and-match you've done between a process on user_clk and a rising edge of user_wren has no proper translation into logic, and breaks the rules of synchronous design. In particular because you never ever want to detect a rising edge of anything else than a clock or a dedicated asynchronous signal, like a reset (it's about glitches).
The if (user_wstrb(0) = '1') part checks the state of user_wstrb's bit 0 at the event of a rising clock (because of the foregoing process / if), and if it's 1, then the register is updated, on that rising clock. Actually, it's an array, so we get a synchronous RAM.
I'm not sure how much this helped. What you really need is to grasp the basics of synchronous design with VHDL, and the xillydemo.vhd example will be crystal clear. That's where I would put the money if I were you.
Regards,
Eli