Questions and discussions about the Xillybus IP core and drivers
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- Simple Test: streamread /streamwrite do not work
by mim » Wed Dec 30, 2020 8:20 am
- 3 Replies
- 80 Views
- Last post by support
Sat Jan 02, 2021 9:31 am
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- PCIe driver couldn't be installed
by Guest » Mon Dec 28, 2020 3:17 pm
- 2 Replies
- 56 Views
- Last post by mim
Fri Jan 01, 2021 9:03 am
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- Xillybus/PCIE crashing after a while of running
by Guest » Tue Nov 03, 2020 3:56 am
- 1 Replies
- 276 Views
- Last post by support
Tue Nov 03, 2020 9:09 am
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- Spartan 6 demo bundle can't regenerate cores
by whennig » Thu Sep 17, 2020 7:37 pm
- 5 Replies
- 1072 Views
- Last post by support
Mon Sep 21, 2020 6:06 pm
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- Xillybus problems on Jetson Nano with Artix 7
by Guest » Thu Sep 03, 2020 12:46 am
- 9 Replies
- 939 Views
- Last post by support
Thu Sep 03, 2020 7:54 pm
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- Using user_mem_8_addr_w with 32bit width?
by Guest » Tue Aug 18, 2020 10:50 pm
- 5 Replies
- 607 Views
- Last post by support
Wed Aug 19, 2020 7:10 am
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- Does Xillybus support Xilinx Alveo U50?
by sarlek » Thu Jul 23, 2020 6:00 pm
- 2 Replies
- 609 Views
- Last post by sarlek
Thu Jul 23, 2020 6:30 pm
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- Integrating xilly bus with custom IP
by Guest » Thu Jul 02, 2020 8:56 am
- 1 Replies
- 496 Views
- Last post by support
Thu Jul 02, 2020 9:07 am
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- Is clk 50 and clk 125 required?
by Guest » Tue Jun 02, 2020 12:05 am
- 1 Replies
- 663 Views
- Last post by support
Tue Jun 02, 2020 5:17 am
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- Synchronous vs asynchronous
by andylgh » Sun May 24, 2020 11:47 am
- 4 Replies
- 1083 Views
- Last post by andylgh
Mon May 25, 2020 11:55 am
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- mem read interface question
by andylgh » Wed May 20, 2020 1:35 pm
- 13 Replies
- 2557 Views
- Last post by andylgh
Fri May 22, 2020 10:46 pm
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- windriver install problem
by andylgh » Tue May 19, 2020 11:58 am
- 7 Replies
- 1506 Views
- Last post by andylgh
Wed May 20, 2020 1:27 pm
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- ZC706 Available upon request?
by andylgh » Mon May 18, 2020 1:44 pm
- 1 Replies
- 767 Views
- Last post by support
Mon May 18, 2020 3:45 pm
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- kintex 7 fpga support pcie x8,5Gbps per lane?
by andylgh » Sat May 16, 2020 7:23 am
- 1 Replies
- 886 Views
- Last post by support
Sat May 16, 2020 7:41 am
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- xillybus over pcie support zynq7000 device or not?
by andylgh » Mon May 11, 2020 12:31 pm
- 2 Replies
- 1262 Views
- Last post by andylgh
Wed May 13, 2020 2:28 pm
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- Xilly kernel driver does not bind to more than one LimeSDR
by Guest » Tue Mar 31, 2020 4:52 am
- 3 Replies
- 2856 Views
- Last post by support
Tue Mar 31, 2020 3:41 pm
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- VC707 board with Xillybus on PCIe GEN3
by tozkoparan » Fri Feb 28, 2020 7:48 am
- 3 Replies
- 2661 Views
- Last post by support
Fri Feb 28, 2020 8:36 am
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- Not able to write data to FPGA (Virtex 7)
by Guest » Sun Feb 23, 2020 3:13 pm
- 3 Replies
- 2249 Views
- Last post by support
Mon Feb 24, 2020 10:16 am
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- No response from FPGA. Aborting
by jeasinema » Thu Sep 22, 2016 3:45 pm
- 6 Replies
- 5099 Views
- Last post by Tariq
Wed Feb 12, 2020 1:18 pm
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- Using Revision B/XL/XXL in the demo bundle
by tomyam9 » Wed Jan 15, 2020 6:48 pm
- 1 Replies
- 1676 Views
- Last post by support
Wed Jan 15, 2020 7:08 pm
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- Am I preventing Xillybus/PCIe from establishing a link?
by Guest » Tue Sep 11, 2018 7:15 pm
- 11 Replies
- 4679 Views
- Last post by support
Fri Dec 13, 2019 11:06 am
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- xillybus reading data problem
by Guest » Thu Nov 28, 2019 9:10 am
- 7 Replies
- 2827 Views
- Last post by support
Thu Dec 05, 2019 1:49 pm
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- about read32 operation
by phdwong » Mon Nov 18, 2019 2:36 am
- 1 Replies
- 1753 Views
- Last post by support
Mon Nov 18, 2019 8:09 am
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- Questions regarding connection to Xillybus FIFO
by Guest » Mon Nov 04, 2019 10:05 pm
- 2 Replies
- 1951 Views
- Last post by rsabedra
Wed Nov 06, 2019 3:58 pm
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- Simple read/write memory interface
by Guest » Sun Oct 20, 2019 1:49 am
- 1 Replies
- 1671 Views
- Last post by support
Sun Oct 20, 2019 4:06 am
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