Xillybus
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- [Synth 8-493] no such design unit 'sw_fifo'
by Guest » Wed Sep 03, 2014 8:26 am - 3 Replies
- 2738 Views
- Last post by support
Wed Sep 03, 2014 1:08 pm
- [Synth 8-493] no such design unit 'sw_fifo'
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- Speed of writing data from host program to FPGA FIFO
by Cristian8 » Fri Aug 15, 2014 6:59 pm - 1 Replies
- 1796 Views
- Last post by support
Fri Aug 15, 2014 7:26 pm
- Speed of writing data from host program to FPGA FIFO
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- LOOK UP TABLES
by jja » Thu Aug 14, 2014 1:40 pm - 1 Replies
- 1300 Views
- Last post by support
Thu Aug 14, 2014 2:06 pm
- LOOK UP TABLES
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- Writing data to FPGA FIFO from host program
by Cristian8 » Tue Aug 12, 2014 10:38 pm - 1 Replies
- 1632 Views
- Last post by support
Wed Aug 13, 2014 6:43 am
- Writing data to FPGA FIFO from host program
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- Xillybus does not met timing
by Guest » Thu Jul 31, 2014 8:33 pm - 1 Replies
- 2023 Views
- Last post by support
Fri Aug 01, 2014 6:52 am
- Xillybus does not met timing
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- canit find xillybus_read_8
1, 2by apna » Wed Jun 04, 2014 4:42 am - 11 Replies
- 5371 Views
- Last post by support
Wed Jul 23, 2014 7:16 am
- canit find xillybus_read_8
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- Linux driver concurrent periodic DMA transfers
by Ves » Thu Jul 17, 2014 5:49 pm - 1 Replies
- 1728 Views
- Last post by support
Thu Jul 17, 2014 6:45 pm
- Linux driver concurrent periodic DMA transfers
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- generating xillybus core for 2 lanes on Kintex
by Guest » Mon Jul 14, 2014 2:55 pm - 4 Replies
- 2794 Views
- Last post by Guest
Mon Jul 14, 2014 6:53 pm
- generating xillybus core for 2 lanes on Kintex
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- Error with 32-bit Memory Writing
by Guest » Tue Jul 08, 2014 10:59 pm - 2 Replies
- 1466 Views
- Last post by Guest
Thu Jul 10, 2014 4:45 am
- Error with 32-bit Memory Writing
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- How to get data from FIFO?
by Cristian8 » Thu Jul 03, 2014 5:45 pm - 3 Replies
- 2669 Views
- Last post by support
Sun Jul 06, 2014 5:06 am
- How to get data from FIFO?
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- fifo.c integration
by Guest » Thu Jun 12, 2014 6:10 pm - 6 Replies
- 4329 Views
- Last post by support
Wed Jun 25, 2014 9:01 pm
- fifo.c integration
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- pcie-xilinx memory buffer size
by Guest » Tue Mar 11, 2014 2:35 pm - 1 Replies
- 1296 Views
- Last post by support
Tue Mar 11, 2014 2:44 pm
- pcie-xilinx memory buffer size
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- I am getting too good results!
by Guest » Wed Mar 05, 2014 4:28 pm - 3 Replies
- 2054 Views
- Last post by support
Wed Mar 05, 2014 11:00 pm
- I am getting too good results!
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- Async streaming in Xillybus
by Guest » Fri Feb 28, 2014 12:54 am - 1 Replies
- 1540 Views
- Last post by support
Fri Feb 28, 2014 1:07 am
- Async streaming in Xillybus
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- PCIe data rate
by svedach » Sat Feb 08, 2014 6:35 pm - 5 Replies
- 4127 Views
- Last post by support
Sun Feb 09, 2014 10:48 am
- PCIe data rate
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- Xillybus bandwidth can't reach more than 75MB/s
1, 2by mjuzwiak » Tue Aug 06, 2013 11:58 am - 10 Replies
- 42558 Views
- Last post by support
Thu Aug 08, 2013 11:04 am
- Xillybus bandwidth can't reach more than 75MB/s
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- pci express endpoint on an fpga based board connected to PC
by Guest » Fri Jun 29, 2012 5:23 am - 2 Replies
- 6199 Views
- Last post by Guest
Mon Aug 20, 2012 12:58 pm
- pci express endpoint on an fpga based board connected to PC
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