Xillybus
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- Capturing data from a PMOD
by Guest » Fri May 01, 2015 4:51 pm - 1 Replies
- 820 Views
- Last post by support
Fri May 01, 2015 7:24 pm
- Capturing data from a PMOD
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- xillycapture.vhd download
by Guest » Sat Apr 18, 2015 6:56 pm - 2 Replies
- 897 Views
- Last post by Guest
Sat Apr 18, 2015 7:17 pm
- xillycapture.vhd download
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- Channel limit
by Guest » Thu Apr 16, 2015 10:31 am - 2 Replies
- 879 Views
- Last post by Guest
Fri Apr 17, 2015 8:29 am
- Channel limit
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- Cygwin streamwrite "Failed to open devfile: Is a directory
by stdoubleu » Tue Apr 14, 2015 12:11 pm - 4 Replies
- 1491 Views
- Last post by stdoubleu
Wed Apr 15, 2015 8:29 am
- Cygwin streamwrite "Failed to open devfile: Is a directory
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- Software accessible register
by Cristian8 » Mon Mar 30, 2015 4:39 pm - 1 Replies
- 876 Views
- Last post by support
Mon Mar 30, 2015 4:47 pm
- Software accessible register
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- Explicitly Flushing Asynchronous Streams
by danielyxie » Fri Mar 13, 2015 4:34 pm - 8 Replies
- 2525 Views
- Last post by support
Thu Mar 26, 2015 8:17 pm
- Explicitly Flushing Asynchronous Streams
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- Xillybus VC707 125MHz x4 Lane Width
by mohdamir » Tue Mar 24, 2015 10:40 am - 4 Replies
- 1218 Views
- Last post by mohdamir
Tue Mar 24, 2015 3:01 pm
- Xillybus VC707 125MHz x4 Lane Width
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- Replacing mem with a dual port ram
by arash » Sat Nov 01, 2014 1:44 pm - 5 Replies
- 1862 Views
- Last post by support
Wed Mar 04, 2015 5:06 pm
- Replacing mem with a dual port ram
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- Expected bandwidth in IP Core Factory
by mohdamir » Fri Feb 27, 2015 8:26 pm - 1 Replies
- 823 Views
- Last post by support
Fri Feb 27, 2015 10:34 pm
- Expected bandwidth in IP Core Factory
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- Xillybus VC707 timing constraint not met
by mohdamir » Fri Feb 27, 2015 6:44 pm - 1 Replies
- 779 Views
- Last post by support
Fri Feb 27, 2015 10:30 pm
- Xillybus VC707 timing constraint not met
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- ERROR GETTING STARTED WITH XILLINUX FOR ZYNQ
by Guest » Fri Feb 13, 2015 2:39 pm - 4 Replies
- 1330 Views
- Last post by support
Fri Feb 13, 2015 4:22 pm
- ERROR GETTING STARTED WITH XILLINUX FOR ZYNQ
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- Maximum send 255 of 32-bit data (1020 Bytes)
by mohdamir » Thu Jan 29, 2015 1:11 pm - 1 Replies
- 660 Views
- Last post by support
Thu Jan 29, 2015 5:17 pm
- Maximum send 255 of 32-bit data (1020 Bytes)
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- sending out Signal through Ethernet
by Guest » Thu Jan 29, 2015 9:39 am - 1 Replies
- 640 Views
- Last post by support
Thu Jan 29, 2015 5:06 pm
- sending out Signal through Ethernet
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- Host to FPGA basics
by Guest » Sat Jan 17, 2015 12:20 am - 1 Replies
- 766 Views
- Last post by support
Sat Jan 17, 2015 7:00 am
- Host to FPGA basics
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- Using IP Cores with Xillybus Core
by Guest » Fri Dec 12, 2014 8:04 am - 1 Replies
- 1046 Views
- Last post by support
Fri Dec 12, 2014 8:19 am
- Using IP Cores with Xillybus Core
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- read the values from the SD card
by Guest » Wed Dec 03, 2014 1:18 pm - 2 Replies
- 723 Views
- Last post by Guest
Tue Dec 09, 2014 10:54 am
- read the values from the SD card
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- DMA, Buffers, and streams
by Guest » Fri Nov 07, 2014 4:06 am - 1 Replies
- 1653 Views
- Last post by support
Fri Nov 07, 2014 8:19 am
- DMA, Buffers, and streams
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- pcie and xillybus
by apna » Mon Feb 03, 2014 3:27 pm - 3 Replies
- 2899 Views
- Last post by support
Tue Oct 14, 2014 5:03 am
- pcie and xillybus
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- Instantiating <something> from unknown module <something els
by Guest » Fri Oct 03, 2014 10:26 am - 2 Replies
- 1569 Views
- Last post by Guest
Sat Oct 04, 2014 3:33 pm
- Instantiating <something> from unknown module <something els
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- questions regarding xillybus and DMA
by Guest » Wed Aug 20, 2014 2:48 am - 9 Replies
- 3019 Views
- Last post by support
Fri Oct 03, 2014 8:43 am
- questions regarding xillybus and DMA
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- [Synth 8-493] no such design unit 'sw_fifo'
by Guest » Wed Sep 03, 2014 8:26 am - 3 Replies
- 1504 Views
- Last post by support
Wed Sep 03, 2014 1:08 pm
- [Synth 8-493] no such design unit 'sw_fifo'
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- Speed of writing data from host program to FPGA FIFO
by Cristian8 » Fri Aug 15, 2014 6:59 pm - 1 Replies
- 1060 Views
- Last post by support
Fri Aug 15, 2014 7:26 pm
- Speed of writing data from host program to FPGA FIFO
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- LOOK UP TABLES
by jja » Thu Aug 14, 2014 1:40 pm - 1 Replies
- 608 Views
- Last post by support
Thu Aug 14, 2014 2:06 pm
- LOOK UP TABLES
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- Writing data to FPGA FIFO from host program
by Cristian8 » Tue Aug 12, 2014 10:38 pm - 1 Replies
- 928 Views
- Last post by support
Wed Aug 13, 2014 6:43 am
- Writing data to FPGA FIFO from host program
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- Xillybus does not met timing
by Guest » Thu Jul 31, 2014 8:33 pm - 1 Replies
- 1321 Views
- Last post by support
Fri Aug 01, 2014 6:52 am
- Xillybus does not met timing
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