Question: Down to the TLP: How PCI express devices talk (Par

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Question: Down to the TLP: How PCI express devices talk (Par

Postby Guest » Wed May 06, 2020 7:27 pm

I apologize I don't have much background in PCIe so I was using this document to get an easier start into it.

Under the "A sample write packet" section of the document, I am unsure what is meant by the phrase

So the packet was transmitted as 0x40000001, 0x0000000f, 0xfdaff040, 0x12345678.

"The Address field is simply the address to which the first data DW is written. Well, bits 31-2 of this address. Note that the two LSBs of DW 2 in the TLP are zero, so DW 2 actually reads the write address itself. Multiply 0x3f6bfc10 by four, and you get 0xfdaff040."

Is there something in the PCIe specification that explains the significance of those last two LSB being 0? What is meant by "reads the write address" itself, what is the significance of mentioning that?

Er, the multiply by 4 part confuses me too as I am unsure of the context there.

I would greatly appreciate any help here.

Thank you.
Guest
 

Re: Question: Down to the TLP: How PCI express devices talk

Postby support » Wed May 06, 2020 7:51 pm

Hello,

The PCIe spec requires that the the address, as given in the third word of the TLP packet, is 32-bit aligned, so the two LSBs of this word are always zero. Byte granularity is handled by the bit enable flags.

And if the wording is confusing, it boils down to that the actual address that is accessed is 0xfdaff040. So on a computer with MMU turned off, it could be the result of a C program saying

*((unsigned int *) 0xfdaff040) = 0x12345678;

Hope this clarified.

Eli
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