Arria 2GX PCI Express RECEIVES WRONG DATA

Comments and questions to the author of the "Down to the TLP" posts (Eli Billauer)

Arria 2GX PCI Express RECEIVES WRONG DATA

Postby Guest » Mon Feb 18, 2013 10:53 am

When I run the default Altera application "Chaining DMA" and send a counter data (2KBytes i.e 0x0000000100000000 - 0x000001FF000001FE ) from the software application side , the data is properly received from 0x0000000100000000 - 0x000000FF000000FE then the sop is valid for more than one pulse , the sop remains high till the rx_valid is high and i lose the data around 20h bytes i.e 0x0000010000000000 - 0x000001200000119 . this keep repeating and is inconsistent. it does vary from lose of 20h bytes and some time 16h bytes.

The IP is generated for

ARRIA2GX 260
lane - x1
maximum payload - 256
desired performance for receiving request - MAXIMUM

BAR REGISTERS
Bar 0 - 32 bit non-prefetchable
Bar 1 - 32 bit non-prefetchable
Bar 2 - 32 bit non-prefetchable


Any idea why the sop is getting corrupted n data lost.. ??
Guest
 

Re: Arria 2GX PCI Express RECEIVES WRONG DATA

Postby support » Mon Feb 18, 2013 12:24 pm

I can't comment on Altera's test application, since I've never tried it.

But it seems like you're using 64-bit addressing on the PCIe bus. I've seen problems with that with some PC hardware. You may want to retry this in 32-bit more (disabling DAC in the driver).

I hope this helps,
Eli
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Re: Arria 2GX PCI Express RECEIVES WRONG DATA

Postby Guest » Mon Feb 18, 2013 12:34 pm

thanks eli for your reply. will look into it.

We are running it on a Windows XP PC (32 bit) .

Is it the addressing error which causes the sop to be continuously high ??
My TLP header does receive an format type as 4A which indicates the 3DW Cpld and get at the pcie side only an 32bit address and the rest 32 bit is a as zeros.
Guest
 

Re: Arria 2GX PCI Express RECEIVES WRONG DATA

Postby support » Mon Feb 18, 2013 12:41 pm

Again, I can't comment on signals that are specific to Altera's test design. But the fact that Windows itself runs 32 bits doesn't say anything about the length of the TLP headers (3DW vs. 4DW). Actually, maybe it does (I'm don't know Windows that well), but I would check what is actually transmitted.
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Re: Arria 2GX PCI Express RECEIVES WRONG DATA

Postby Guest » Tue Feb 19, 2013 5:07 am

Hey Eli

Thanks for your reply.

Could you please let us know how to disable the DAC from the driver end. ??
Guest
 

Re: Arria 2GX PCI Express RECEIVES WRONG DATA

Postby support » Tue Feb 19, 2013 10:59 am

There is a bit in each BAR entry (usually called "64-bit capable") which says if the respective memory region can be mapped to a 64-bit address or not. If this bit indicates 32-bit addressing only, there is no reason for the server to generate 4DW-header TLPs.

This is relevant, because the only reason the root complex could have to produce an address-based TLP is for accessing the BAR-mapped portions of the device. Completions are addressed by the bus address ID.

In theory, the root complex could send a 4DW-header TLP to a 32-bit addressable BAR, with an address that maps into 32 bit space. I have to admit, that looking at the specification, I didn't find any clear statement about whether the root complex is allowed to do this or not. But having seen some "interesting" PC hardware, I wouldn't feel safe to assume that turning the 64-bit off would prevent 4DW-header TLPs, even if the spec said it should.

As for manipulating this issue with the driver -- I'm sorry, I have no idea. The 64-bit capable bit in the BAR is your best shot, I think, and I would follow that up by monitoring what arrives at the hardware.

Eli
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