Why and how 4KB boundary limit is imposed?

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Why and how 4KB boundary limit is imposed?

Postby Guest » Tue Apr 23, 2013 11:05 am

Hi

Could you please furnish the details,

1. Why 4KB boundary limit is imposed on the PCIe/AXI transfers?
2. How this limit is calculated, Please provide the math behind this limit with a given address bus width?


Thanks
Arun Kumar N
arunkumarnellur@gmail.com
Guest
 

Re: Why and how 4KB boundary limit is imposed?

Postby support » Tue Apr 23, 2013 2:44 pm

Hello,

Why the limit exists is something one should ask those who wrote the standards. Anyhow, a lot of things on computer hardware is bounded to 4 kB. Maybe it's because DDR memory rows are 4 kB in size, so crossing such a boundary would force the memory controller to run two row fetch operations. But once the limitation is set, I'm not sure it helps asking why they did it.

Defining the limit formally is simpler: A bus request's address range must be such, that all involved addresses differ only in their 12 least significant bits. For 32-bit addressing, this means that all involved addresses ANDed with 0xfffff000 must have the same value.

Or, if a bus request starts at address START and has length LENGTH in bytes (LENGTH=1 is one byte), then we require, for 32-bit addressing, that
START & 0xfffff000 == (START + LENGTH - 1) & 0xfffff000

Hope this helped.
Eli
support
 
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