How to build PCIe IP core on custom board

Comments and questions to the author of the "Down to the TLP" posts (Eli Billauer)

How to build PCIe IP core on custom board

Postby Guest » Mon Apr 29, 2013 9:37 pm

Hi,

I am new to FPGA and am trying to build PCIe on a custom board with only 1 lane available. The board is based on Virtex 6 and will be used for data acquisition. I have tried to use the xillybus demo on ML605 board and the demo runs perfect. However, when I tried to use the IP core factory to build a custom IP core, there is no place to define the number of lanes.

So is there any documentation showing how and where to change or modify the number of the lanes to be used? Where is the file to define the custom board pin out and other configuration (like bus_clk?)

Thanks for any help!

Jason
Guest
 

Re: How to build PCIe IP core on custom board

Postby support » Mon Apr 29, 2013 9:51 pm

Hello,

I understand that you want to run in an 1x configuration rather than Virtex 6's default of 4x. I suggest requesting a demo bundle for 1x directly through email.

But I'll explain the principle for the sake of understanding:

The Xillybus IP core relies on the PCIe front end from Xilinx (or Altera for their FPGAs). The number of lanes should be changed in the front end core.

A direct consequence is that the number of PCIe pins from the PCIe front end core is reduced. The xillybus.v and xillydemo modules should be edited to reduce the signals that connect these external pins with the PCIe core.

In some cases, there is a need to update the timing constraints and also remove some pin placements. The best way to tell is looking how the constraints file produced by Xilinx' PCIe core changes when the lane setting is changed from 4x to 1x.

Note that all of these changes have nothing to do with Xillybus itself.

Since the Xillybus IP core doesn't care what happens beyond the PCIe front end core, there is no problem configuring and downloading the regular Virtex-6 IP core. The only thing to keep in mind is that the actual allowed bandwidth is reduced to around 200 MB/s in each direction, as with Spartan-6.

If the host supports Gen2 PCIe, it's possible to achieve around 400 MB/s as well.

Hope this helped.
Eli
support
 
Posts: 619
Joined: Tue Apr 24, 2012 3:46 pm

Re: How to build PCIe IP core on custom board

Postby Guest » Tue Apr 30, 2013 3:49 am

Thanks for your direction. I have sent emails for the request.
Guest
 


Return to General PCIe

cron