How do PCIe writes start?

Comments and questions related to the "Down to the TLP" pages

How do PCIe writes start?

Postby Guest » Mon Jul 01, 2013 7:06 pm

In part one you show an example of writing a DW to an endpoint by filling out the 4 DW header. I understand that you write to all 4 DWs 0 through 3 with the desired data, but what I don't understand is how and when the data gets sent. I don't see a "send TLP packet bit" to tell the PCIe controller when to send the a newly formed TLP packet. If I was creating a write request TLP that had 128 bytes, how does the controller know that I'm finished writing and that the packet is ready to be sent? Is there an order in which the DWs have to be written?

thanks

gary
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Re: How do PCIe writes start?

Postby support » Mon Jul 01, 2013 7:21 pm

Hi,

If you're in the business of actually generating TLP packets, you're most likely writing HDL code to be implemented to be a bitstream for an FPGA or silicon on an ASIC. If you're wearing that hat, you'll have an IP core (the logic world's library function) to work with. That IP core's specification tells you exactly how to communicate the information about the packet to be transmitted. For exampe, Xilinx will ask you to form it as an AXI stream packet. Altera will tell you to use their Avalon interface.

Those interfaces have wires that are separate from the data wires (plus quite a few other control wires). The common way is to indicate the last clock containing data for a specific packet by asserting a wire saying called something like "end of packet". That will make the PCIe controller begin handling the packet

If you're just running software, a packet is created when a PCIe-enabled processor issues a read or write request on the bus. In that case, you don't have anything to do with the packet formation. You just perform a read or write access to say, memory space, and the packet is generated automatically by the processor's logic.

I hope this clarified things.
Eli
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Re: How do PCIe writes start?

Postby Guest » Mon Jul 01, 2013 7:40 pm

My TLPs are written by softwware to an onboard PCIe controller. But it's not an atomic operation writing 4 DWs at a time. How does the controller know when I'm done writing all the needed data for a TLP? It can't send a packet until I fill in all 4 DWs.

thanks,

Gary
Guest
 

Re: How do PCIe writes start?

Postby support » Mon Jul 01, 2013 7:45 pm

Could you please be specific about what controller you have there? I've never heard about a PCIe controller run by software that lets you form the TLP packets one by one. Unless it's some testing equipment.
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Re: How do PCIe writes start?

Postby Guest » Mon Jul 01, 2013 8:35 pm

The new OMAP processor from TI has 2 PCIe controllers built in. They can be configured as a root complex or as an endpoint. There is 265MB of memory mapped space for each controller. So if it is configured as an root complex and I want to send 128 bytes (32 DWs) to a connected and ready endpoint, I make a series of writes to the memory mapped header space simliar to your example, except that I write a value of 32 into the length field and write 128 bytes (32 DWs) after writing the destination address into DW 3. Writing 3 DWs of header data and 32 DWs of payload data is not going to be an atomic operation out to memory. So how does the PCIe controller know when I'm finished writing the header and writing all of payload data? My processor could even get interrupted by a higher priority task while I'm writing the header and the data payload.

I haven't come across any other control register that instructs the PCIe controller to send the MWr to the endpoint.

thanks,

gary
Guest
 

Re: How do PCIe writes start?

Postby support » Mon Jul 01, 2013 9:13 pm

Well, the answer lies in that processor's user guide. There should be detailed instructions on how to initiate an operation on the bus.

And still, I would be very surprised if it turned out that you should actually set up the TLPs fields. In a processor context, this is usually done by setting one register to the beginning of the buffer you want to send, another to the start address you want to send it to, and a third saying how many bytes or whatever to send. What triggers the transmission, and how you get notified that it has finished is specific to the processor. My hunch is that TI just extended one of their DMA controllers and turned it into a machine that sends PCIe packets.

Anyhow, I can't help you much further. This is really a matter of reading the manual.

Regards,
Eli
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