DMA from FPGA to Host

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DMA from FPGA to Host

Postby Guest » Tue Feb 25, 2014 11:36 pm

I have been working on an FPGA board for a while, and I have only used simple memory map read/write to communicate from host to FPGA. As reads are very inefficient this way, I have to use DMA for my new project. I have tried everything I could find and think of, yet it doesn't work. So, my first question is that if DMA from FPGA to Host is feasible on any architecture?

To be more specific, I am using Terasic DE2-i150 board. You can see the block diagram on page 4 of this document: http://www.intel.com/content/dam/www/pu ... ev-kit.pdf

As you can see, the CPU memory is directly connected to CPU, while I have seen other architectures that memory is connected to the root complex. I don't understand if it matters or not. Can I still do DMA operations from FPGA to CPU memory, if memory is not connected to the root complex?!

If it is not possible, then I'm doomed. But if its, then I would provide some information about my implementation and hopefully get a direction to go on.

Thanks,
M.P.
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Re: DMA from FPGA to Host

Postby support » Tue Feb 25, 2014 11:45 pm

Hello,

Intel x86 CPUs maintain cache coherency with the DMA operations. That's why the CPU has to be between the FPGA and the memory.

And since this happens to be the Xillybus forum -- have you considered trying out Xillybus' IP core, even for the sake of seeing that DMA is possible? There's a demo IP core for Cyclone IV for immediate download. ;)

Regards,
Eli
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Re: DMA from FPGA to Host

Postby Guest » Wed Feb 26, 2014 12:14 am

Thank you for your prompt answer Eli.

I am not sure if that was a yes or no.

I have tried the xillybus project you mentioned. The MegaWizard Plugin Manager gives me an error when I choose pcie_c4_1x.v file according to the instructions. Can you help me with that?! I'm using Quartus 13.0.1. If you could help me fixing this, I would be an even huger fan of your work :)

Thanks
Guest
 

Re: DMA from FPGA to Host

Postby Guest » Wed Feb 26, 2014 12:17 am

Sorry, forgot to mention the error. It says: "Specify a valid MegaWizard-generated variation file"
Guest
 

Re: DMA from FPGA to Host

Postby support » Wed Feb 26, 2014 12:44 am

Hi,

The answer was yes -- DMA is possible. PCIe is completely pointless without DMA.

As for the issue with Quartus, it expects you to pick "IP Compiler for PCI Express" (for Cyclone V it would have been "Cyclone V Hard IP for PCI Express 13.0"). This used to be set up automatically in Quartus 12.0.

Best regards,
Eli
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Re: DMA from FPGA to Host

Postby Guest » Wed Feb 26, 2014 1:30 am

Thanks again,

I want to ask a question about my implementation if it's fine. I have read the Altera PCIe IP Compiler documentation to understand how the translation table works. I have configured the IP Compiler to use dynamic address translation; In my device driver, I use dma_alloc_coherent function to get a memory region as DMA buffer, then I write dma_handle (bus address) of this region to the translation table of the device (I think I do this part correctly, so I skip the details). I initialize the memory in kernel, then send a signal to invoke the device, the device writes something to the TXS of PCIe IP Compiler using an Avalon MM Master interface. According to the docs, this write operation should be translated to a PCIe write packet. But after the handshakes are done, I don't see the right values in the memory. I see the same values I initialized in the kernel!

Please tell me if I'm missing something in this scenario. I have double-checked everything. I'm not an expert in device drivers. Maybe I have missed something there? Are there any necessary steps to grant DMA access, other than allocating the memory and sending the pointer over? That's my best guess.

Thanks
Guest
 

Re: DMA from FPGA to Host

Postby support » Wed Feb 26, 2014 10:13 am

Hi,

Apparently, you're using the Avalon-MM interface, which I'm not familiar with, so I'm afraid I can't help you much with this,

Eli
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Re: DMA from FPGA to Host

Postby Guest » Wed Feb 26, 2014 2:56 pm

Thanks Eli,

It was really helpful. I would appreciate if you tell me how to fix the problem with Quartus. Would it work if I install an older version?
Guest
 

Re: DMA from FPGA to Host

Postby support » Wed Feb 26, 2014 3:05 pm

It will work with Quartus 12.0. But didn't my answer above help?
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Re: DMA from FPGA to Host

Postby Guest » Wed Feb 26, 2014 5:25 pm

Sorry, I didn't realize you updated that answer.

In the instruction, it says I should choose "Edit an existing custom megafunction variation". When you choose "Edit ..." the you can only pick up a file and picking pcie_c4_1x.v throws the error. I can pick "IP Compiler for PCI Express" if you choose to create a new megafunction, and then I have to enter all the parameters. I am not sure what you mean by picking "IP Compiler for PCI Express", because there is no option for that in edit.

P.S. I tried to edit the megafunction name inside the file and it didn't work either.
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