The Xillybus Forum

Hi,
I am trying to understand Atomic operation supported in PCIe gen3. I read about atomic operations in general and found out that these operations are supported for avoiding clashes when accessing shared resources via multiple sources.

In legacy pci these operations were supported using Lock transaction. i.e. RC can initiate lock request in response to atomic request from software. As path is locked no other transaction can flow through the fabric. So chances of conflict in accessing shared resource is not there.

Now in PCIe we have atomic TLPs for the same. What I am not able to understand is that how it is made sure that shared resource is not being accesses from other source? Also is there special hardware unit used to support atomic operations?

Please correct where my understanding is incorrect.

Thanks.

Hello,

Unfortunately, all I can say is that I hope someone shows up and answers your question. I never got anywhere near this issue. For what it's worth, this is the first time I hear anyone interested in locking on the PCIe bus, so maybe that's a hint in itself...

Good luck,
Eli

Hi eli,
So do you have any idea how atomic instructions from software are handled by RC?

Thanks

Ah, I wasn't clear enough above. Unfortunately no -- I have no idea about atomic operations.

Eli