Hello,
First of all thanks for the great articles, I'm pretty new to all this so they have been a big help. I have a few questions though, any help with these would be appreciated.
Firstly, what is the definition of the PCIe Root Complex as I have read multiple online, is it more comparable to the old fashioned North Bridge, including devices like the memory controller and the PCI host controller etc., or is it just the PCI host controller? (I believe it is the former)
Secondly, on a basic level, does a PCIe system have a PCIe host controller just like an old fashioned PCI system, this PCIe host controller is the bridge that bridges between the local bus and PCIe tree?
Thirdly, I was reading this really old article from HP - http://tinyurl.com/ocp6awt and towards the end it says - " The PCI 2.2 specification (pages 202-204) dictates that root PCI bus must be allocated one block of MMIO addresses" I have looked in the PCI 2.2 specs on pages 202 - 204 and can't find anything that says the root PCI bus must be allocated one block of addresses. I know the MMIO region is usually from TOLUD to 4GB but I didn't think the PCI specs enforced it to be in one block, is this just an error?
Fourthly, I doubt anyone can answer this as but you may have an idea, looking at the recent Intel CPU datasheets it mentions that regions such as ISA legacy area and the Firmware memory range area are sent to DMI, do these regions go through the PCIe host controller or straight to the DMI? In a modern CPU what is the range that actually goes through the PCIe host controller, is it just from TOLUD to (4GB - 20MB) and other memory regions go to DMI directly?
I drew this diagram below -
As far as I can gather it would look something like that. I realise I should have labelled it Host Bridge and not 'Root Complex'
Any help with the above questions would be greatly appreciated. I'm happy to send a donation via PayPal if you want.
Thanks.