Generic PCIe/PCI questions

Comments and questions related to the "Down to the TLP" pages

Generic PCIe/PCI questions

Postby Guest » Thu Jul 31, 2014 7:29 pm

Hello,

First of all thanks for the great articles, I'm pretty new to all this so they have been a big help. I have a few questions though, any help with these would be appreciated.

Firstly, what is the definition of the PCIe Root Complex as I have read multiple online, is it more comparable to the old fashioned North Bridge, including devices like the memory controller and the PCI host controller etc., or is it just the PCI host controller? (I believe it is the former)

Secondly, on a basic level, does a PCIe system have a PCIe host controller just like an old fashioned PCI system, this PCIe host controller is the bridge that bridges between the local bus and PCIe tree?

Thirdly, I was reading this really old article from HP - http://tinyurl.com/ocp6awt and towards the end it says - " The PCI 2.2 specification (pages 202-204) dictates that root PCI bus must be allocated one block of MMIO addresses" I have looked in the PCI 2.2 specs on pages 202 - 204 and can't find anything that says the root PCI bus must be allocated one block of addresses. I know the MMIO region is usually from TOLUD to 4GB but I didn't think the PCI specs enforced it to be in one block, is this just an error?

Fourthly, I doubt anyone can answer this as but you may have an idea, looking at the recent Intel CPU datasheets it mentions that regions such as ISA legacy area and the Firmware memory range area are sent to DMI, do these regions go through the PCIe host controller or straight to the DMI? In a modern CPU what is the range that actually goes through the PCIe host controller, is it just from TOLUD to (4GB - 20MB) and other memory regions go to DMI directly?

I drew this diagram below -

Image

As far as I can gather it would look something like that. I realise I should have labelled it Host Bridge and not 'Root Complex'

Any help with the above questions would be greatly appreciated. I'm happy to send a donation via PayPal if you want.

Thanks.
Guest
 

Re: Generic PCIe/PCI questions

Postby support » Fri Aug 01, 2014 7:10 am

Hi,

I'll try to take your questions one by one:

The definition of the root complex -- well, if there are many definitions, then there's probably no "the definition". To me, the root complex is the entity on the bus that enumerates the others. It's the one that gave itself address zero. On Intel architectures, the question is somewhat theoretic, because it fakes an internal PCI bus for its built-in peripherals, so whatever reaches the outside world (i.e. the real PCI/PCIe bus) is always through a switch or bridge. Or so it appears on the bus topology.

And yes, I suppose any processor has a bridge between its internal bus and the PCIe bus, through some bridge.

As for the MMIO registers -- I suppose that they meant the registers for configuring the root complex itself. I also suppose that any PCIe root complex is designed having such registers, even though one could theoretically configure it through, say an I2C bus. The only question is why one would do that.

As for your forth question -- just go lspci on a Linux machine, and you'll get a list of what's mapped on the PCI/PCIe controller. What doesn't appear on that list, isn't. In fact, it's possible that things that do appear in the lspci list isn't really attached to a real PCIe bus, but to an internal bus, faking the behavior of a PCIe device for software compatibility. But if a legacy device doesn't appear on this list -- it's surely not connected to the PCIe bus.

Regards,
Eli
support
 
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Re: Generic PCIe/PCI questions

Postby Guest » Fri Aug 01, 2014 2:59 pm

Thanks eli, appreciate it.

1. Thanks.

2. I though so, on the Haswell datasheet it says that PCI device 0 is the "memory controller / host bridge"

3. Thanks.

4. That's the thing, in the PCH there is the LPC controller for example that decodes the firmware range. The LPC controller is a PCI device on 'Bus 0' but doesn't have the standard PCI BARs at offset 10h. I'm just not sure of say when the CPU wants to read from the firmware, does this go through the host bridge or directly to DMI as a non PCIe transaction.
Guest
 


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