Xillybus enable signals and Fifo connections

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Xillybus enable signals and Fifo connections

Postby Cristian8 » Tue Feb 24, 2015 6:49 pm

Hi Eli and all,
I am using a state machine to take data off of an asynchronous FIFO and serialize it out onto pins. As seen in my code below, the asynchronous FIFO is 32x512 with the Xillybus user device file: user_w_write_32_data as it's input. After running my code, I am receiving a correct 32 bit sequence out however, it then skips a random amount of bits before I receive another correct 32 bit sequence. If my set up is correct, I would expect to see at least a sequence of 32x512 correct bits corresponding to the size of the FIFO. This leads me to wonder if I am using the enable signals incorrectly? Any help is much appreciated. Thank you very much.

Code: Select all
512
   //All signals from and to the Xillybus IP core must be clocked with the bus_clk supplied by the core itself. //Zynq-based platforms typically have a clock of 100MHz
   //This is not to say, that data sources and sinks need to be clocked with bus_clk. In a typical application, one side of an asynchronous FIFO is connected to the Xillybus core, and is therefore
   clocked with bus_clk.
   
   async_fifo_32x512 fifo_32 //FIFO created using Xilinx FIFO Generator Wizard
   (
      .rst(initial_reset), //!user_w_write_32_open), //initial_reset),//!user_r_read_32_open),
      .wr_clk(bus_clk),
      .rd_clk(fifo_clk),//////////////////////////////////////////////////////////////////////////////////////////////////////////////clock
      .din(user_w_write_32_data) //user_w_write_32_data),// data input is attached to the XILLYBUS user device file: user_w_write_32_data
      .wr_en(1'b1), //1'b1),//user_w_write_32_wren), //always write to FIFO
      .rd_en(enable_reading),
      .dout(fifo_data_wire),
      .full(fifo_full), //user_w_write_32_full), //fifo_full),
      .empty(fifo_empty)
   );

   reg bert_clk = 1'b0;
   reg [5:0] cnt_32_idx = 6'd0;
   reg [31:0] bert_32_serial = 32'd0;
   reg bert_data = 1'b0;
   reg [20:0] delay_cnt = 21'd0;
   localparam HOLD = 21'd650; // Total_Cycles - 1
   
   //signals for FIFO
   reg initial_reset = 1'b0; //.rst
   //bus_clk //.wr_clk
   wire fifo_clk = clk_100; //.rd_clk
   //user_w_write_32_data //.din // Wires related to /dev/xillybus_write_32
   //user_w_write_32_wren //.wr_en //Wires related to /dev/xillybus_write_32
   reg enable_reading;//.rd_en
   wire[31:0] fifo_data_wire;//.dout
   wire fifo_full;  //.full
   wire fifo_empty; //.empty
   
   //Logic to take data off of FIFO and serialize onto pins

   //Declare State Registers
//   reg [2:0] nextstate = 3'b000;
   reg [3:0] state = 4'b0000;
   //reg [2:0] currstate = 3'b000;
   //reg read_reg = 1'b0;
   //Declare States
//   parameter state0 = 3'b001;
//   parameter state1 = 3'b010;
//   parameter state2 = 3'b100;
   parameter state0 = 4'b0000;
   parameter state1 = 4'b0001;
   parameter state2 = 4'b0010;
   parameter state3 = 4'b0100;
   parameter state4 = 4'b1000;

////STATE MACHINE

always @(posedge fifo_clk) begin
      case(state)
         state0: begin
            enable_reading = 1'b1;
         end
         state1: begin
            bert_32_serial = fifo_data_wire;
            cnt_32_idx = 6'd0;
         end
         state2: begin
            enable_reading = 1'b0;
            bert_data = bert_32_serial[0];
            bert_32_serial = bert_32_serial >> 1;
            cnt_32_idx = cnt_32_idx + 6'd1;
         end
         state3: begin
            bert_clk = 1'b1;
            delay_cnt = delay_update(delay_cnt);
         end
         state4: begin
            bert_clk = 1'b0;
            delay_cnt = delay_update(delay_cnt);
         end
      endcase
   end
   
   function [20:0] delay_update;
      input [20:0] count;
      
      if (delay_cnt > HOLD) begin
         delay_update = 0;
      end
      else begin
         delay_update = count + 1;
      end
   endfunction 
Cristian8
 
Posts: 5
Joined: Mon Jun 30, 2014 4:22 pm

Re: Xillybus enable signals and Fifo connections

Postby support » Tue Feb 24, 2015 7:51 pm

Hello,

What stands out in your code is that you assign a constant logic '1' on the FIFO's wr_en input. As a result, the FIFO is written to all the time, regardless of whether the data in its din port is valid. The correct way is to connect this port to user_w_write_32_wren -- which you knowingly diverted from for whatever reason.

This explains why you have junk data between valid elements.

You may do whatever you want on the application's side of the FIFO, but the connection with the XIllybus IP core must follow the API, or weird things happen...

Regards,
Eli
support
 
Posts: 760
Joined: Tue Apr 24, 2012 3:46 pm


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