Sniffing TLPs from PCIe Device

Comments and questions related to the "Down to the TLP" pages

Sniffing TLPs from PCIe Device

Postby dbakoyiannis » Thu Feb 26, 2015 9:32 pm

Dear Eli,

I have read your blog post about sniffing TLPs from a PCIe device.
I am working on a project on KC705 development board and what I would like to do is count TLPs that the board receives over PCIe from the Linux host.
If I understand correctly, your sniffer is a piece of hardware that captures the TLPs that the PCIe block of the FPGA receives or transmits.
I suppose something similar to your sniffer would be what I need for counting TLPs.
Would it be possible to share any information or hints on how to start making my own sniffer?
Thank you in advance!
dbakoyiannis
 
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Re: Sniffing TLPs from PCIe Device

Postby support » Thu Feb 26, 2015 9:59 pm

Hello,

If you're using a 64-bit interface, it's quite simple -- since each TLP packet is an AXI stream packet, you may count the number of "last" events.

So it goes something like (in Verilog)

Code: Select all
always @(posedge user_clk_out)
  if (s_axis_tx_tready && s_axis_tx_tvalid && s_axis_tx_tlast)
    count_outgoing <= count_outgoing + 1;

for counting outgoing packets. Change the tx with rx, and it counts ingoing packets.

For a 128-bit interface, it becomes slightly trickier, but it boils down to counting SOF or EOF signals, based upon the same principle.

Regards,
Eli
support
 
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Re: Sniffing TLPs from PCIe Device

Postby dbakoyiannis » Fri Feb 27, 2015 7:46 am

Hello,

Thank you very much for your help!
I will start working on that!

Regards,
Dimitrios
dbakoyiannis
 
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Re: Sniffing TLPs from PCIe Device

Postby dbakoyiannis » Fri Feb 27, 2015 1:32 pm

Hello again,

It seems that this code can sniff the AXI Stream interface of the PCIe Block of the FPGA.
What I understand is that when the three signals that you mention (s_axis_tx_tready, s_axis_tx_tvalid, s_axis_tx_tlast) are asserted this means that there is a TLP.
If it is appropriate to ask, how can you get information about the headers of each TLP?
In my case it would be desirable to also get header information in order to experiment with deadlocks that might take place in a PCIe transaction.
Thank you!

Dimitrios
dbakoyiannis
 
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Re: Sniffing TLPs from PCIe Device

Postby support » Fri Feb 27, 2015 2:02 pm

Hi,
dbakoyiannis wrote:Hello again,
What I understand is that when the three signals that you mention (s_axis_tx_tready, s_axis_tx_tvalid, s_axis_tx_tlast) are asserted this means that there is a TLP.

Well, sort of. When these signals are high together, the last element of the TLP is present on the tdata wires. Since each TLP has one such last element, counting these events counts the TLPs.

If you want to gather the TLP information, I suggest connecting the tdata (or rdata) wires to the data input ports of a FIFO. The FIFO's write enable should be (s_axis_tx_tready && s_axis_tx_tvalid). As a result, each element in the bus is written to the FIFO.

You probably want to connect the tlast wire as well, possibly concatenated with the data word, so the boundaries between the packets are logged. But it's possible to do without these, as the length of the packets can be deduced from the TLP's headers.

How to get the FIFO's content handy is a different topic. I used a Xillybus stream to transport its content to a PC (which is very easy). As Xillybus' traffic caused TLP traffic, I ended up with a system that sniffs its own traffic, but that was fine for the purpose of exploring what's going on.

Regards,
Eli
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