The Xillybus Forum

While sending a read request, completer ID is not giver, but only the address is given. If there are multiple PCIe switches, how the request is forwarded to the correct PCIe switch without having its completer ID?

Hello,

Read and write requests are indeed routed by the address only. This routing is possible, because each switch is assigned a range of the address space for itself and the endpoints on its downstream ports. This assignment takes place during enumeration. It also has the information about which address ranges are assigned to each of its downstream ports.

So when a packet arrives at a switch with only an address, the switch first checks if this address is mapped to one of its downstream ports. If it is, the packet is routed to the relevant port. If not, the packet goes to the upstream ports, i.e. towards the root complex. Sooner or later it arrives at a switch (possibly the root port's) that has a downstream port covering the address, and the packet begins traveling downwards, until it reaches the endpoint.

Regards,
Eli