Latency to send few data from uP to FPGA

Comments and questions related to the "Down to the TLP" pages

Latency to send few data from uP to FPGA

Postby tom78 » Tue Jun 09, 2015 9:37 am


I am sending a small burst of data (32 Bytes) from the uP to the FPGA Virtex7 through PCIe GEN3 x8.
With an AMD processor, I see that the FPGA is receiving 1 TLP of 2x32bytes word (4 ns between each word, the first word has the address + 16 Bytes and the second only the last 16 Bytes).
With a XEON processor, I see 2 TLPs with a latency of 90 ns between them (the first TLPs has address+16 data and the second Address+16 data).

AMD processor is quite old (4 years) and XEON is very new.

Does someone know why I have this poor performances with XEON processor, and does I miss any FPGA IP configuration?

I am on LINUX and I use exactly the same driver for the 2 cases.

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Re: Latency to send few data from uP to FPGA

Postby support » Tue Jun 09, 2015 12:31 pm


It's not clear what you mean with the uP sending bursts to the FPGA. As far as I know, there is no way to make an x86 processor send a burst of data, except completing a read request. Or is this what you did? Because if so, it's indeed quite possible different processors behaved differently.

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