Clarification of Memory, IO and configuration

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Clarification of Memory, IO and configuration

Postby Guest » Tue Dec 01, 2015 1:50 am

Hi Eli/all,
first off all thanks for the blog. It is really very helpful. I have a basic question. PCI has three address spaces - Memory, IO and configuration. Could you please explain what is the different between Memory address space and IO address space. why we need to two different memory and IO address space ? It seems that while configuration of the PCIe device some part of it configured as memory address space and some other part as IO address space. How do you make such decision which address to map IO or memory ?

Thanks
Praveen
Guest
 

Re: Clarification of Memory, IO and configuration

Postby support » Tue Dec 01, 2015 7:46 am

Hi,

There are indeed three address spaces for a PCI/PCIe device:
  • The configuration space contains a data structure, which informs the host about the device's capabilities and status. The host sets some registers in this address space to configure the device (in particular, it assigns the device's bus address and BAR regions by writing to these registers).
  • The memory space is where accesses take place when the host performs a memory read or write, as in plain C's *addr = data, where addr points at an address that is mapped to the device.
  • The I/O space is a legacy support feature, which allows backward compatibility with rather ancient peripherals. For example, the parallel port 0 is traditionally mapped to I/O ports 0x378-0x37a. No new design should rely on this space. Peripherals mapped to the I/O space are usually implemented directly on the processor itself or its companion chip.
Aside from being an ancient leftover, the I/O space requires an inp or outp opcode in x86 assembly language, and may not be supported at all by non-x86 processors. And unlike a memory space write, writes to I/O ports require that the processor waits until the device acknowledges the read (by sending a completion on the PCIe bus). In terms of today's processors, that slows down things considerably. Writing to memory space, on the other hand, is fire-and-forget (i.e. a posted transaction).

So the bottom line is that I/O space should be used only for the sake of following an already established convention on how to access that type of device. Otherwise there is no reason to use it.

Regards,
Eli
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Joined: Tue Apr 24, 2012 3:46 pm

Re: Clarification of Memory, IO and configuration

Postby Guest » Wed Dec 02, 2015 5:47 am

Thanks alot Eli for your detailed explanation. It helps.
I'm new to PCIe. Could you please help me to clarify following as well ?
I appreciate your help.

1. Why only Memory Write transactions are posted and why not IO Write transaction ?
2. Difference between Cfg0 and Cfg1 packets,read or write . why we have two types configuration packets. ?
3. Some application example why huge amount traffic need to go through PCIe end point ?
Guest
 

Re: Clarification of Memory, IO and configuration

Postby support » Wed Dec 02, 2015 6:37 am

Hello,

I've found little interest in I/O ports as well as configuration packets, so I'm afraid I can't add much on those topics. I suppose that I/O transfers are posted because the way I/O ports are used. That is, that software expects the hardware to be updated before execution continues. Say, if the software disables a certain interrupt by writing to the port, it may assume that no interrupt will be issued after that.

As for applications requiring heavy PCIe traffic -- it seems like graphic adapters in particular, but also SATA adapters, Ethernet and USB (USB 3.0 in particular) can generate significant traffic.

Regards,
Eli
support
 
Posts: 760
Joined: Tue Apr 24, 2012 3:46 pm


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