PCIe Payload size limit
Posted:
Hi there,
Im working on an fpga pci device, and i noticed that reading is faster than writing.
when looking at lspci -vv
i see that my kernel is giving my device only 256 MaxPayload, I understand that the kernel does this according to the slowest device on the path between my fpga to the root complex.
what can i do to figure out what device is limiting my payload size?and how can i fix this?
Thanks alot
Im working on an fpga pci device, and i noticed that reading is faster than writing.
when looking at lspci -vv
i see that my kernel is giving my device only 256 MaxPayload, I understand that the kernel does this according to the slowest device on the path between my fpga to the root complex.
what can i do to figure out what device is limiting my payload size?and how can i fix this?
Thanks alot