FIFO to Design Empty

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FIFO to Design Empty

Postby Guest » Fri Mar 18, 2016 1:03 am

I have used the Xillybus with a 32-to-16 FIFO to stream data from the PC to my design. By placing an ILA at the output of the FIFO and capturing the data and empty signal, I am finding that the FIFO is empty about half the time. I am only running my design at 10MHz which seem like it should almost never go empty given the speed of the PCIe? Any suggestions?


Re: FIFO to Design Empty

Postby support » Fri Mar 18, 2016 8:53 am


The most likely explanation is that you're not pushing data fast enough from the host. You may want to check the process' CPU consumption (with "top" in Linux).

This happens when the data buffer that is allocated and used in the user program is too small, so write() is called too often. Each write() is a system call with its processing overhead, and this wastes CPU as the data rate increases.

The sample programs given by Xillybus use a small buffer in order to skip the malloc() part, but for a serious application, they should be something like 128kB - 512kB.

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