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Write Transaction and Read Transaction

PostPosted: Sat Mar 26, 2016 6:36 am
by Guest
Dear Sir/Madam,
I am unable to understand how data is being routed to a specific device in the PCIe hierarchy, by only defining address in the packet. Does this mean address specified in the packet is unique for every device or there is some device selection mechanism before sending read/write packet.

Thanks and Regards,
Ap

Re: Write Transaction and Read Transaction

PostPosted: Sat Mar 26, 2016 8:43 am
by Guest
Address in the Memory transaction.

Re: Write Transaction and Read Transaction

PostPosted: Sat Mar 26, 2016 9:25 am
by support
Hello,

One can view a PCIe bus as a tree of switches. Each switch has one upstream port, which is directed towards the root complex (the CPU or its memory chipset in most cases), and several downstream ports, which go to endpoints or other switches. There's always at least one such switch, which is the one next to the root complex.

When the host boots, it performs an enumeration on the PCIe bus (typically done by the BIOS on PCs). Among others, this enumeration includes assigning a segment of physical addresses to each of the downstream ports of each switch, as required (according to BAR entries, or a bit more complicated for PCIe switches / bridges).

So each switch has a memory segment allocated to each of its downstream ports. If a certain downstream port is connected to an endpoint, this memory segment consists of the address range(s) required by this endpoint (possibly with some holes). If there's a switch connected to this port, the address range is allocated so as to satisfy that switch' needs for covering the downstream ports it has.

Now to routing: Whenever a TLP packet that is routed by memory address reaches any of these switches, the switch checks if the address is within one of the ranges allocated to its downstream ports. If so, the packet is routed to that downstream port. If not, it goes to the upstream port.

This simple routing method allows routing packets towards the root complex for addresses that aren't covered by any endpoint, as well as peer-to-peer routing, possibly without going through the root complex' switch.

Regards,
Eli

Re: Write Transaction and Read Transaction

PostPosted: Sat Mar 26, 2016 11:53 am
by Guest
Thank you.

Re: Write Transaction and Read Transaction

PostPosted: Mon Nov 18, 2019 9:30 am
by Guest
But isnt PCIe like a DMA? What i mean is, if the host writes to an address in the memory map for PCIe device A, the PCIe takes the data and puts it in the PCIe device A without CPU intervention