Idea needed on PCIe on ML605

Comments and questions to the author of the "Down to the TLP" posts (Eli Billauer)

Idea needed on PCIe on ML605

Postby nagchil » Thu Mar 31, 2016 4:59 am

Hello,

I need an idea of implementation of PCIe endpoint on ML605 board.
My concept is,
I am taking video streaming from at 640*480p to my FPGA, from there i need send that data to PC (host) via PCIe interface.
I have created an endpoint using IP coregen (Xilinx RAM Memory Controller : 6011) and implemented it on a FPGA, When FPGA board is connected to PC it is detected successfully.
Please help me how to give data to that endpoint in FPGA and send it to PC.

I have already seen xapp1052 and implemented as shown..
Everything according to mannual completed successfully..
My actual doubt is..according to the image provided in the attachment..
Image
Middle FPGA is main Controller FPGA..
The data from the all other 4 FPGA's will be tranferred to main Controller FPGA...and that data to be transmitted to PC(host) via PCIe..
The simple endpoint implementation from IP core in main Controller FPGA will not do as required....
So iam asking idea how to transfer data.......

Plz Help me..
nagchil
 
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Re: Idea needed on PCIe on ML605

Postby support » Thu Mar 31, 2016 6:44 am

Hello,

There is more than one way to do it, but since you're asking this question on the Xillybus Forum, the obvious answer is: Use Xillybus' IP core.

Please go to the download section of Xillybus' site and get yourself the demo bundle for ML605. And take it from there.

Regards,
Eli
support
 
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Re: Idea needed on PCIe on ML605

Postby Guest » Fri Apr 01, 2016 3:29 am

hello,
Without installing xillybus driver in linux what kind of device files i will get in /dev/ folder...??
Guest
 

Re: Idea needed on PCIe on ML605

Postby support » Fri Apr 01, 2016 6:34 am

Nothing. That is, none that are related to the FPGA. Just the /dev/ files that belong to other hardware.
support
 
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Re: Idea needed on PCIe on ML605

Postby Guest » Mon May 09, 2016 3:38 am

Hello eli sir,
Greetings of the day,

can i know the communication from FPGA to PC via PCIE..
means how these mapped memory and dev files are arranged...
Guest
 

Re: Idea needed on PCIe on ML605

Postby support » Wed May 11, 2016 12:02 pm

Hello,

If you want some insight on how Xillybus is implemented, you may take a look at Appendix A of this:

http://xillybus.com/downloads/doc/xilly ... _linux.pdf

Regards,
Eli
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Re: Idea needed on PCIe on ML605

Postby nagchil » Tue Jun 07, 2016 5:15 am

hello sir thanks it helps me a lot....
nagchil
 
Posts: 9
Joined: Tue Mar 22, 2016 7:36 am

Re: Idea needed on PCIe on ML605

Postby nagchil » Tue Jun 07, 2016 5:24 am

Hello eli sir,
I am having some doubts..??
1. if i take out the two fifo modules in xillybus design and replace by a BRAM, the xilly bus drivers will work ...???
2. In your document i have seen words like loop back, what does it mean..
3. Mapping of system memory occurs for Memory BAR / IO BAR / Config space or for the all...??
iam a new designer ... so need to know.....these may be small doubts...but plz help me.........
plz suggest me some books/pdfs for PCIE protocol and PCIE Drivers ..
nagchil
 
Posts: 9
Joined: Tue Mar 22, 2016 7:36 am

Re: Idea needed on PCIe on ML605

Postby support » Tue Jun 07, 2016 8:19 am

Hello,

1. You may attach BRAMs to Xillybus by using seekable streams. The issue is detailed in the documentation extensively.
2. Please Google it: https://en.wikipedia.org/wiki/Loopback
3. Xillybus uses Memory BAR, DMA and MSI interrupts for interacting with the host.

Regards,
Eli
support
 
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