BAR memory Mapping for PCIE

Comments and questions to the author of the "Down to the TLP" posts (Eli Billauer)

BAR memory Mapping for PCIE

Postby nagchil » Fri Jul 15, 2016 12:01 pm

Hello eli,
iam using ML605 PCIe design, following xtp044 from xilinx.

In PIO design given by xilinx, i have replaced PIO_MEM_ACCESS.v internal memory with my own two SDP RAM modules(each 128KB), one for tx mem and another for rx mem. I have loaded this memory with a predefined .coe file. In IP Core generation i have used BAR0(128KB) and BAR1(128KB). So from PC(Ubuntu) iam trying to read that data...So i have written a driver...Like this inside probing function,
1. Enable device,
2. Request regions for BAR0&1
3. ioremap (128KB BAR0)
3. ioremap (128KB BAR1)
4.using ioread32 function for reading

So now i am expecting my .coe file values...but iam getting output 0 why..??

I have connected like as shown in diagram below
Image
if that diagram not visible see this link https://forums.xilinx.com/xlnx/attachments/xlnx/PCIe/7741/1/WP_20160715_13_05_06_Pro.jpg
BAR mapped memory is that these tx_bram and rx_bram or anything internal to endpoint....
PLZ can anybody help...i didnt find any exact answer for this..
nagchil
 
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