Read requests to non Root Complex

Comments and questions to the author of the "Down to the TLP" posts (Eli Billauer)

Read requests to non Root Complex

Postby Guest » Thu Jan 26, 2017 2:50 am


I have been doing some experiments to transfer data peer to peer between two PCIe device (NVMe in my case). In this case I have observed that when one PCIe endpoint device sends PCIe read request TLP to another PCIe endpoinr device, the completions start flowing in after a good latency. Whereas when PCIe endpoint device sends read request to host (Root Complex), the completions are almost instantaneous.

As I understand the PCIe Endpoint core and Root Complex cores are not extremely different. The skeleton are almost same and there should be no problem in handling the read requests in either case.

Any idea?

Re: Read requests to non Root Complex

Postby support » Thu Jan 26, 2017 9:10 am


How much latency is "a good latency"? Is it within the spec's allowed range?

It seems quite natural to me that different devices return their answer after different amounts of time. After all, you're requesting the device to fetch some information for you. A root complex (usually the CPU or its memory chip) merely gets it from its DDR memories. An NVMe needs to grab it from a flash memory. Which takes a bit longer, I guess.

So as long as the latencies are within spec, there's nothing to be alarmed about.

Posts: 482
Joined: Tue Apr 24, 2012 3:46 pm

Return to General PCIe