Are the RX and TX paths interdependent at PHY level?
Posted:
Hello,
I'm new to the whole PCIe world. I'm interested in designing a signal boosting Repeater for the PCIe Gen4. Would I need to architect for the lane which would include RX and TX both? Or, can I go for a generic architecture, where I can put repeater chip only on all the RX pairs; and another repeater part on TX pairs?
Am I missing any RX to TX interdependencies, or timing relationships?
I'm new to the whole PCIe world. I'm interested in designing a signal boosting Repeater for the PCIe Gen4. Would I need to architect for the lane which would include RX and TX both? Or, can I go for a generic architecture, where I can put repeater chip only on all the RX pairs; and another repeater part on TX pairs?
Am I missing any RX to TX interdependencies, or timing relationships?