Memory Write Request TLP

Comments and questions to the author of the "Down to the TLP" posts (Eli Billauer)

Memory Write Request TLP

Postby Guest » Fri Mar 31, 2017 9:41 am

Hi all,

I've got a question about the Memory Write Request TLP with Data Payload and 32-bit addressing.
On the tutorial guide Part I it's an example of MWr and Data Payload are placed in DW 3 (unaligned data).
While Altera for their Stratix V claims that this DW 3 is reserved (Appendix A, TLP Packet Format with Data Payload of "Stratix V Hard IP for PCI Express User Guide" - https://www.altera.com/zh_CN/pdfs/literature/ug/ug_s5_pcie.pdf , page 325).
I'm using 256-bit mode with Avalon-ST interface.

Could you please explain me when I can use 3DW header with unaligned data for 256-bit Mem Request?

Thanks,
Dave
Guest
 

Re: Memory Write Request TLP

Postby support » Fri Mar 31, 2017 10:01 am

Hello,

Short answer: You can always use a 3DW header, regardless of whether the data is aligned or not. The PCIe spec forbids the use of a 4DW header for addresses below the 4GB region, so Altera's PCIe block must support that (and indeed it does).

As for how to generate these packets, please refer to figure 8-16 in the document you referenced.

True, in the Appendix A of that document, where they show the TLP format for general information, they chose to put "Reserved" where there is possibly data. Either way, it's not relevant, because the Stratix PCIe block moves the first DW around to (partly) conform with the Avalon-ST view of data alignment. So when preparing the packets for the Avalon-ST interface, it doesn't matter what the actual TLP will look like.

Regards,
Eli
support
 
Posts: 482
Joined: Tue Apr 24, 2012 3:46 pm

Re: Memory Write Request TLP

Postby Guest » Fri Mar 31, 2017 10:25 am

Thank you, it explains a lot.

What do you mean by "the Stratix PCIe block moves the first DW around"?
When I want to send a packet of 3DW header + 160 bit Data from FPGA in one clock cycle - it'll be actually send in 2 clock cycles from Stratix PCIe block because of Avalon-ST alignment?

Regards,
Dave
Guest
 

Re: Memory Write Request TLP

Postby support » Fri Mar 31, 2017 10:41 am

Hello,

What I'm saying is that it doesn't matter how the packets are eventually organized on the PCIe bus -- you need to conform to the packet format given in Altera's user guide.

As for sending 160 bits (5 DWs) of data with a 3 DW header: As shown in figure 8-16, if the address is Qword aligned, it's two clocks indeed. If it's Qword unaligned, you fit it into a single clock.

Regards,
Eli
support
 
Posts: 482
Joined: Tue Apr 24, 2012 3:46 pm

Re: Memory Write Request TLP

Postby Guest » Fri Mar 31, 2017 10:51 am

Great - Thank you, Eli ;)
Guest
 


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