SR-IOV support on Artix-7 FPGA

Comments and questions to the author of the "Down to the TLP" posts (Eli Billauer)

SR-IOV support on Artix-7 FPGA

Postby arindamkhan2003 » Tue Oct 31, 2017 5:13 am


In white paper, WP384 It is written that SR-IOV capability support on all 7-series device. However, at pcie core generation time in Vivado 2016.1, SR-IOV capability is only available for Virtex-7 series device. Even xapp1177 talks about SR-IOV support for only virtex-7 device.

Kindly clarify that is it possible to generate PCIe core for Artix-7 having SR-IOV capability?. If not, it has anything to do with PCIe Gen 3.0 support, because Artix-7 series only supports Gen 2.0.

Also, what I understand from the Virtex-7 PCIe (with SR-IOV) generated code that some ARI capable parameters are passed to PCIE_3_0 primitive. Whether this primitives are not supported on PCIE_2_1?

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