Bus clock

Comments and questions related to the "Down to the TLP" pages

Bus clock

Postby sina » Sat Feb 02, 2019 10:33 pm

Hi. I am using Virtex 7 and I got the xillybus demo for PCIE interface from your website. Could you please tell me what is the default bus clock frequency in your design? Also can I change the bus clock frequency in the file? If yes,what would be the maximum possible value?
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Re: Bus clock

Postby support » Sun Feb 03, 2019 8:01 am


I assume that you refer to bus_clk (and not the clock on the PCIe hardware bus itself).

Xillybus exposes Xilinx' PCIe block's "application clock", which is the clock used for interfacing with the block, as bus_clk. You may hence change it by setting that block's lane and speed settings, as described in the Getting Started guide for Xilinx.

The demo bundle for Virtex-7 has a 250 MHz bus_clk, which is the maximal clock possible. You probably wouldn't benefit from a clock with a higher frequency, as it's getting non-trivial to meet timing.

If you want your own application logic to work with a different clock, use dual-clock FIFOs to interface with Xillybus, so that the side facing Xillybus is clocked with bus_clk, and the one facing your logic is clocked with whatever clock you chose.

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