In PCIe, why there is below restriction?
Section 2.2.7: Requests must not specify an Address/Length combination which causes a Memory Space access to cross a 4-KB boundary.
Consider that you have a BAR of 1MB. The address offset varies from 0x00000 to 0xfffff. I feel it should be okay for someone to give a Memory Request of 128DW to address=0x0000_fff0. It doesn't feel wrong to my intuitions. But why the PCIe Spec/architecture restricts it.
Thank you in advance...
Q: PCIe request to Memory Space crossing 4k boundary
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Re: Q: PCIe request to Memory Space crossing 4k boundary
by support »
Hello,
It's a bit pointless to argue about things that are already written in such a well-established specification. But I can come up with a few situations where this restrictions may simplify the implementation of hardware.
For example, if DDR memories in involved in a DMA read request to the CPU. Reading from a DDR memory involves requesting a DDR row, which typically contains 1024 memory elements. On a 32-bit bus, that's exactly 4 kB/row. So if the read request is ensured not to cross a 4kB boundary, that also ensures that the request can be completed with a single row operation.
Another example I can think of is when there is an IOMMU. Each DMA request to the CPU requires the evaluation against the IOMMU's memory conversion map. This map is arranged according to 4kB pages. The fact that the page boundary is never crossed means that the IOMMU only needs to check one entry.
Knowing that there's only one operation needed often simplifies hardware the implementation considerably. But why they decided on this restriction many years ago is a different question.
Regards,
Eli
It's a bit pointless to argue about things that are already written in such a well-established specification. But I can come up with a few situations where this restrictions may simplify the implementation of hardware.
For example, if DDR memories in involved in a DMA read request to the CPU. Reading from a DDR memory involves requesting a DDR row, which typically contains 1024 memory elements. On a 32-bit bus, that's exactly 4 kB/row. So if the read request is ensured not to cross a 4kB boundary, that also ensures that the request can be completed with a single row operation.
Another example I can think of is when there is an IOMMU. Each DMA request to the CPU requires the evaluation against the IOMMU's memory conversion map. This map is arranged according to 4kB pages. The fact that the page boundary is never crossed means that the IOMMU only needs to check one entry.
Knowing that there's only one operation needed often simplifies hardware the implementation considerably. But why they decided on this restriction many years ago is a different question.
Regards,
Eli
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