Q: PCIe request to Memory Space crossing 4k boundary
Posted:
In PCIe, why there is below restriction?
Section 2.2.7: Requests must not specify an Address/Length combination which causes a Memory Space access to cross a 4-KB boundary.
Consider that you have a BAR of 1MB. The address offset varies from 0x00000 to 0xfffff. I feel it should be okay for someone to give a Memory Request of 128DW to address=0x0000_fff0. It doesn't feel wrong to my intuitions. But why the PCIe Spec/architecture restricts it.
Thank you in advance...
Section 2.2.7: Requests must not specify an Address/Length combination which causes a Memory Space access to cross a 4-KB boundary.
Consider that you have a BAR of 1MB. The address offset varies from 0x00000 to 0xfffff. I feel it should be okay for someone to give a Memory Request of 128DW to address=0x0000_fff0. It doesn't feel wrong to my intuitions. But why the PCIe Spec/architecture restricts it.
Thank you in advance...