pci express endpoint on an fpga based board connected to PC

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pci express endpoint on an fpga based board connected to PC

Postby Guest »

Sir,
I have designed and a PCIe endpoint IP core using VHDL (X1,2.5/5 Gbps). At present the low power states are not developed and Xilinx Virtex6's GTX is used as the PHY.Functional validation of the core is done by integrating my core with Xilinx root complex available from Xilinx ISE13.1 with Questasim. Using Questssim the physical link initalization, speed negotiation, datalink layer initialization and configuration TLP exchanges are monitored.
Then I plugged Xilinx ML605 board with Virtex 6 FPGA on the motherboard of a PC and implemented PCIE endpoint core in it. when I restart the PC, I can see the working of LTSSM, exchange of DLLPs, configuration TLP transfers between the board and the PC through Chipscope analyzer. But most of the time my PC is not booting when PCIE core is available on its PCIe slot, BUT sometimes it is booting and showing 'device initialization error in PCIe slot'. So I doubt some error in the register settings of configuration space.
My intention is to monitor the configuration register space and transfer of some memory read/write request to the endpoint through 'PCI tree'.
For that I would like to know
1. What BIOS will do during PCIe bus enumeration? In which order BIOS access configuration registes? It is found that BIOS is repeatedly reading few registers.
2. Can I work without Low power support in the LTSSM
3. Can I work only with MSI (without INTx)
4. Can we set our own vendor ID (for checking)
5. Is their any standard method for testing PCIe endpoint.I do not have a protocol analyzer
6. Which are the mandatory registers in the Type0 Configuration space.

Will you please provide some relevant information about PCIE endpoint testing and debugging especially regarding configuration space, power management and interrupt mechanisms.

Regards
Jaya S
Senior Engineer
CDAC
Trivandrum,
India.
Guest
 

Re: pci express endpoint on an fpga based board connected to

Postby support »

Hello,

"PC booting sometimes" is something I've heard from some people, mostly those using relatively old PC hardware. For my own curiosity, what is the motherboard model you tried it on?

I would initially suggest to try it on another computer. It's not a solution to the problem, but it will at least let you see that the board is talking with you.

What the BIOS does at boot time is pretty much up to the BIOS version. There is a certain sequence defined in the specification, but there is much room for implementation-specific variations.

And yes, I would suggest playing around with the Vendor ID, Product ID, and the class data. I've had someone telling me that changing the base class did matter.

As for MSI-only settings, this is the way the Xillybus IP core is configured (no legacy interrupts) and it works well. Some old motherboard chips have cranky support of MSI, so the operating system may not cooperate. But I haven't had any indication that choosing MSI only would be a reason for a no-boot.

Regarding the rest of your questions, I'm afraid I can't help much.

If you manage to solve your issue without changing the computer, I will be most curious knowing what you did.

Eli
support
 
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Re: pci express endpoint on an fpga based board connected to

Postby Guest »

Hi, I have worked on PCIe projects on Altera and Xilinx FPGA's (VHDL and soft-CPU) including MSI only solutions. Since i'm more comfortable in a Windows environment i'm using Jungo WinDriver to "test"/debug MSI interrupts (and other basic functionality). However a protocol analyzer is extremely valuable in (lowlevel) debugging.

Concerning your boot problem with ML605. I should also suggest trying another computer. If the problem still exists, i still have a working "basic bus master dma pcie endpoint" example design for ML605 in VHDL.
Guest
 


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